Interfaces - 1.0 English - PG427

Cached DRAM Binary CAM LogiCORE IP Product Guide (PG427)
Document ID
PG427
Release Date
2023-10-18
Version
1.0 English

All AXI4-Stream interfaces use the following three ports: tvalid, tdata, and tready.

Software Interface – DBSI

Using a 32b wide AXI4-Lite bus, DBSI receives the management commands from software. Supported commands are:

Insert
Add a new entry to the CDBCAM. The required arguments are the key and the response.
Delete
Remove an entry from the CDBCAM. The required argument is the key.
Update
Modify the response part of an entry in the CDBCAM. The required arguments are the key and the new response.

Management operations are atomic operations. Complete entries are written to the CDBCAM database before they are made active (valid). The database is kept in a persistent state at all times in order for ongoing lookups to never fail.

Lookup Interface – LI

The Lookup Interface can be divided into two separate interfaces.

LI_Req
An AXI4-Stream slave interface, where the CDBCAM receives key lookup requests.
LI_Resp
An AXI4-Stream master interface, where the CDBCAM presents responses to lookup requests.

The CDBCAM database stores the (key, response) entries and performs matching by processing a Lookup operation. If the lookup key matches the key of any entry, then match indication and the response are presented on the output. The API software guarantees that two entries using identical keys cannot be inserted, so only one match is possible. If the lookup key does not match the key of any entry, a no match indication and a default response are presented on the output. CDBCAM supports a software configurable default response.

DRAM Interface – DMI

Using a wide AXI4 bus, CDBCAM issues write and read commands to DRAM where all entries are stored. CDBCAM interfaces to DRAM through the AMD Versal™ AXI4 NoC. CDBCAM supports the following AXI4 NoC-based DRAM types: HBM and DDR4. NoC configurations for each memory type are detailed in the following table.

Table 1. DRAM Configuration Parameters
DRAM Type DRAM Clock Freq. [MHz] NoC NMU Data Bus Width DRAM Address Mapping DRAM channels per CDBCAM NoC NMUs per DRAM Channel
DDR4 2400 512 RBC-BG0 1 1
HBM 2400 256 RBC
  • PCS: 1, 2, 4, or 8
  • NMUs: 2, 4, 8, or 16
 2, 4, or 8
Note: The number of NoC interfaces used by the IP will be automatically selected. A single interface is available for the DDR4 DRAM type. Two interfaces are available for the HBM DRAM type.