Example Design - 1.0 English - PG427

Cached DRAM Binary CAM LogiCORE IP Product Guide (PG427)

Document ID
PG427
Release Date
2023-10-18
Version
1.0 English

The following sections show the example design block designs for both DDR and HBM:

DDR Memory

Figure 1. CDBCAM Example Design for DDR Memory

Address translation between CDBCAM and DDR memory is performed by axi_noc_0.

The configuration depicted in the following figure could be used as a reference for remapping.

Figure 2. Remapping Reference (DDR)

HBM

Figure 3. CDBCAM Example Design for HBM

Address translation between CDBCAM and HBM is performed by axi_noc_0.

The configuration depicted in the following figure could be used as a reference for remapping.

Figure 4. Remapping Reference (HBM)