BCS RAM memory Error Correcting Code
All memories in the BCS database are Error Correction Coding (ECC) protected. There are eight additional ECC bits for every address in a 64-bit wide memory. The eight additional bits are used only for ECC and cannot be used for storage. 64-bit wide memories are always referenced in this document (even though 72 bits are used).
A scrubbing mechanism starts regularly (at a 1 ms interval) and reads every memory address of the BCS in the background using idle cycles. If a single-bit error is detected during scrubbing, the error is corrected permanently by writing the corrected data back to the memory. Single-bit errors detected during lookup operations are corrected dynamically. If a double-bit errors is detected during lookup, there is no match.
DRAM Error Correcting Code
This Versal memory IP core has optional Error Correcting Code (ECC) support. As ECC scrubbing and ECC correction are part of the Versal IP hardware, you are responsible for configuring the IP hardware to use these features. Detailed descriptions of these mechanisms are available in the AXI High Bandwidth Controller LogiCORE IP Product Guide (PG276).