DRAM Interface Ports - 1.0 English - PG427

Cached DRAM Binary CAM LogiCORE IP Product Guide (PG427)
Document ID
PG427
Release Date
2023-10-18
Version
1.0 English

CDBCAM supports standard AXI4 interface with NoC memory. The interface supported parameters values are:

Table 1. DRAM Interface Parameters
Local Parameter Width Description
AXI_ADDR_W 64 Width of address bus
AXI_ID_W 1 Width of ID bus
AXI_LEN_W 8 Width of burst length bus
AXI_DATA_W DDR4 – 512

HBM – 256

 Width of data bus
AXI_STRB_W AXI_DATA_W/8 Width of write strobes bus
Note: A single interface is available for the DDR4 DRAM type. 2, 4, 8, or 16 interfaces are available for the HBM DRAM type. In this case, all DRAM ports are available as a 2-D array with two rows corresponding to the two AXI4 interfaces.
Table 2. DRAM Interface
Port Name I/O Width Clock Description
AXI_ARADDR O AXI_ADDR_W key_clk AXI4-full read request address.
AXI_ARBURST O 2 key_clk AXI4 read request burst type.
AXI_ARID O AXI_ID_W key_clk AXI4 read request ID.
AXI_ARLEN O AXI_LEN_W key_clk AXI4 read request burst length.
AXI_ARSIZE O 3 key_clk AXI4 read request burst size.
AXI_ARVALID O 1 key_clk AXI4 read request valid.
AXI_AWADDR O 1 key_clk AXI4 write request address.
AXI_AWBURST O 2 key_clk AXI4 write request burst type.
AXI_AWID O AXI_ID_W key_clk AXI4 write request ID.
AXI_AWLEN O AXI_LEN_W key_clk AXI4 write request burst length.
AXI_AWSIZE O 3 key_clk AXI4 write request burst size.
AXI_AWVALID O 1 key_clk AXI4 write request valid.
AXI_BREADY O 1 key_clk AXI4 write response ready.
AXI_RREADY O 1 key_clk AXI4 read response ready.
AXI_WDATA O AXI_DATA_W key_clk AXI4 write request data.
AXI_WLAST O 1 key_clk AXI4 write request last data burst.
AXI_WSTRB O AXI_STRB_W key_clk AXI4 write request data strobe.
AXI_WVALID O 1 key_clk AXI4 data write request valid.
AXI_ARREADY I 1 key_clk AXI4 read request ready.
AXI_AWREADY I 1 key_clk AXI4 address write request ready.
AXI_BID I AXI_ID_W key_clk AXI4 write response ID.
AXI_BRESP I 2 key_clk AXI4 write response status.
AXI_BVALID I 1 key_clk AXI4 write response valid.
AXI_RDATA I AXI_DATA_W key_clk AXI4 read response data.
AXI_RID I AXI_ID_W key_clk AXI4 read response ID.
AXI_RLAST I 1 key_clk AXI4 read response last data burst.
AXI_RRESP I 2 key_clk AXI4 read response status.
AXI_RVALID I 1 key_clk AXI4 read response valid.
AXI_WREADY I 1 key_clk AXI4 data write request ready.