Customizing and Generating the Core - 1.0 English - PG427

Cached DRAM Binary CAM LogiCORE IP Product Guide (PG427)

Document ID
PG427
Release Date
2023-10-18
Version
1.0 English

This section includes information about using AMD tools to customize and generate the core in the AMD Vivado™ Design Suite.

The following are instructions on how to deploy the Cached DRAM Binary CAM using the standalone CDCAM IP.

CDBCAM IP version 1.0 (cdcam_v1_0) is released as part of the AMD Vivado™ Design Suite. The CDBCAM IP can be instantiated in Vivado in one of two different ways: using the IP integrator or using the IP catalog.