Core Configuration - 1.0 English

Cached DRAM Binary CAM LogiCORE IP Product Guide (PG427)

Document ID
PG427
Release Date
2023-10-18
Version
1.0 English

The CDBCAM IP core configuration fields are shown in the following figure, and are defined below.

Figure 1. Core Configuration Fields
Component Name
The name of the core component to be instantiated. The name must begin with a letter and be composed of the following characters: a to z, A to Z, 0 to 9 and ‘_’.

Interface Specification

CLOCKING_MODE
The use of a separate memory clock is optional. In SINGLE_CLOCK mode all logic (except a small amount of control logic on the AXI4-Lite domain) is clocked on the lookup interface clock.
LOOKUP_INTERFACE_FREQUENCY
Sets the lookup clock to between 15 MHz and 400 MHz in DUAL_CLOCK mode, and a maximum of 250 MHz in SINGLE_CLOCK mode.
MEMORY_INTERFACE_FREQUENCY
Sets the memory interface frequency to a value between 15 and 250 MHz when clock mode is set to DUAL_CLOCK.

Parameters

DRAM_TYPE
Choice of DDR4 (default) or HBM. Determines the memory controller connected to the NoC. DDR4 uses one AXI MEM port of 512 bit data width while HBM uses two or more AXI MEM ports of 256 bit data width.
NUM_ENTRIES
Enter the number of key/response entries that you want in the CDBCAM (depth). The range is from 8192 to 60397977 entries although there are limitations within that range depending on other parameter choices made. Default is 1887436 (approx. 90% of 2M).
Table 1. Limitations
DRAM_TYPE Versal Device Type Entry size (KEY_WIDTH + RESPONSE_WIDTH ) < 512 NUM_ENTRIES range
DDR4 any Yes 8192 – 60,397,977
DDR4 any No 8192 – 60,397,977
HBM xcvh1582, xcvh1782 Yes 8192 – 60,397,977
HBM xcvh1582, xcvh1782 No 8192 – 60,397,977
HBM xcvh1522, xcvh1542, xcvh1742 1 Yes 8192 – 60,397,977
HBM xcvh1522, xcvh1542, xcvh1742 1 No 8192 – 30,198,988
  1. These devices have 512 MB per PC, thus have the limitation for number of large size entries.
Note: When stored in DRAM, entry size (key width plus response width plus one status bit) is rounded up to the nearest round number of bits – 512 or 1024. The maximum number of entries in the CDBCAM is a key configuration parameter to set. When NUM_ENTRIES is set, it is important to know the following:
  1. Up to 90% of available memory can be used for storing the entries.
  2. Dedicated DRAM size will be rounded up to the nearest power of 2.

For example:

For entry size of 453b, each entry would take 512b (64B) of DRAM space. If the required number of entries is 7 million, the occupied DRAM space will be at least 64B x 7 x 10^6 / 90% = 497,777,778. When rounded up to the nearest power of 2, dedicated DRAM size must be at least 512MB.

KEY_WIDTH
The width (unpadded) of the key value in bits. The default is 64 bits wide. The range is 10 to 992 inclusive.

KEY_WIDTH + RESPONSE_WIDTH should not exceed 1016.

RESPONSE_WIDTH
The width (unpadded) of the response value in bits. Default is 64 bits wide. Range is 1 to 1006 inclusive.

KEY_WIDTH + RESPONSE_WIDTH should not exceed 1016.

DEFAULT_RESPONSE_VALUE
When a lookup misses, the value set in this parameter will be output. Width of parameter corresponds with RESPONSE_WIDTH.
CACHE_SUPPORT
Using a cache in CDBCAM results in a higher average lookup rate (see Performance) and lower latency for systems that benefit from caching (that is, when the frequency of lookups for some keys are much higher than for the others). This improvement comes at the cost of FPGA resources. You can choose not to use the cache, or when using it, to choose between different options that are determined by the required lookup rate and FPGA resource cost. The reference point in the case of the lookup is the AXI4S clock key_clk frequency. You can determine the lookup rate to be full, half, or a quarter of that frequency. You can also choose whether to use URAM or block RAM memory primitives for cache storage. In the case of URAM, full rate builds a cache that can store up to 16K entries, 8K for half rate and 4K for quarter rate. When block RAM is used these sizes are eight times smaller respectively.
REQUIRED_DRAM_PHYSICAL_SIZE
This is not a configurable parameter, but it provides a calculation of the minimum DRAM size required to fulfil the number of entries entered, with the key and response widths considered.
UPDATE_MODE
In situations where access to a powerful CPU with lots of available memory is not available, hardware controlled content update can be a good choice. It requires little CPU power and memory, as the full execution of inserts, updates, and deletes is performed by hardware. This comes at a cost in FPGA resources.
NUM_PCS
Determined by key width, response width, and number of entries. For HBM, the number of PCS can be increased above the minimum.