Required Constraints
This section is not applicable for this IP core.
Device, Package, and Speed Grade Selections
AMD Versal™ design families are supported.
Clock Frequencies
The CDBCAM has three independent clocks:
-
key_clk - Used for the core logic and the interface to the NoC. The frequency is set using the parameter LOOKUP_FREQUENCY_INTERFACE and can range between 15 MHz and 400 MHz.
-
s_axi_aclk - For reading and writing key/response pairs to the CDBCAM over an AXI4-Lite interface. Up to 150 MHz.
-
mem_clk - Used for interface to the NoC. Up to 250 MHz.
Clock Management
The frequency for key_clk is configured
using the LOOKUP_FREQUENCY_INTERFACE parameter in the Vivado IDE.
In dual clock mode, the frequency for mem_clk is configured using the
MEMORY_FREQUENCY_INTERFACE parameter in the Vivado IDE.
The example design has generated clock constraints for
key_clk, mem_clk (DUAL_CLOCK) and
s_axi_aclk.
Clock Placement
This section is not applicable for this IP core.
Banking
For DDR IOBs, placement is dependent on the Versal device part number used. Refer to Configuring Memory IP in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.