Clocking - 1.0 English

Cached DRAM Binary CAM LogiCORE IP Product Guide (PG427)

Document ID
PG427
Release Date
2023-10-18
Version
1.0 English

All timing analysis has been performed on -2M speed grade. The CDBCAM clock domains are shown in the following table.

Table 1. CDBCAM Clocking
Clock Max. Frequency Description
s_axi_aclk 150 MHz This clock is used for table management. The AXI management interface has a completely asynchronous relationship with the lookup interface.
key_clk 400 MHz The rest of the CDBCAM logic including Lookup Request/Response interface and its related logic.
mem_clk 250 MHz NoC interface and its related logic.