Cache Flow - 1.0 English - PG427

The BCAM Cache Subsystem (BCS) provides potentially significant increase in performance at the cost of FPGA memory and logic. The BCS stores frequently matched entries and, in the case of a hit, provides a much faster response than the DBCAM on its own. The cache operates as follows:

1. A key is looked up in the BCS.
2. If the key is found, the response is provided.
3. If the key is not found in the BCS, the lookup request is passed onto the DBCAM.
4. If the key is found in the DBCAM, the hit indication is provided together with the response. In addition, an attempt is made to insert the entry into the BCS for the next potential lookup.
5. If the key is not found in the DBCAM, the miss indication is provided with the default response.
6. Whenever an entry is deleted or updated in the DBCAM, a delete command is issued to the BCS.

The BCS can provide a significant benefit in terms of performance when the data traffic has patterns in which some lookup keys are searched more frequently than others. As mentioned, the cost of such an improvement in performance is in FPGA resources (block RAM or URAM).