| LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family | VCK5000 |
| Supported User Interfaces | AXI4-Lite CSR Interface |
| Resources | See Performance and Resource Use |
| Provided with Core | |
| Design Files | XO files/connection files/AIE library file |
| Example Design | Verilog |
| Constraints File | Xilinx Design Constraints (XDC) |
| Supported S/W Driver | XRT |
| Tested Design Flows 1 | |
| Design Entry | Vivado® Design Suite |
| Simulation | N/A |
| Synthesis | Vivado Synthesis |
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