SGDMA Descriptor Control Register (0x18) - SGDMA Descriptor Control Register (0x18) - 1.0 English

SGDMA Descriptor Control Register (0x18) - SGDMA Descriptor Control Register (0x18) - 1.0 English - PG344

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID

PG344

Release Date

2022-05-20

Version

1.0 English

Table 1. SGDMA Descriptor Control Register (0x18)
Bit Index	Default	Access Type	Description
		W1C	Bit descriptions are the same as in SGDMA Descriptor Control Register (0x10).