The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 05/20/2022 Version 1.0 | |
| AXI4-Stream C2H Ports | Updated AXI4-Stream C2H Port Descriptions table. |
| Function Map Table | Updated. |
| AXI4-Lite Master Ports | Updated Config AXI4-Lite Memory Mapped Read Master Interface Port Descriptions table. |
| AXI4-Stream C2H Ports | Updated AXI4-Stream C2H Port Descriptions table. |
| QDMA VF Address Register Space | Updated QDMA VF Address Register Space table. |
| Descriptor Bypass Mode | Updated. |
| 04/26/2022 Version 1.0 | |
| General updates | Updated for Versal Premium ACAP support. |
| Debug Guide | New section. |
| 12/20/2021 Version 1.0 | |
| Minimum Device Requirements | Added new section. |
| C2H Channel 0-3 AXI4-Stream Interface Signals | Added m_axis_h2c_tkeep_x. |
| Basic Tab | Added recommendations regarding selecting the correct GT starting quad before lane rate and width. |
| QDMA Global Ports | Added csr_prog_done. |
| AXI4-Stream C2H Ports | Updated s_axis_c2h_ctrl_ecc[6:0]. |
| User Interrupts | Update usr_irq_in_vec. |
| PCIe MISC Tab in Root Port Mode | New content added. |
| Debugging chapters | Added link to debugging answer record. |
| Upgrading | Updated link for migration information. |
| Limitations | Updated content, and moved to an appendix. |
| 04/27/2021 Version 1.0 | |
| Initial release. | N/A |