If your board is designed to use the same PCIe edge connectors to operate with CPM and PL PCIE, then we recommend using PS reset using the Control, Interface and Processing System (CIPS) IP core. For more information, see the Versal ACAP CPM Mode for PCI Express Product Guide (PG346).
If your board is designed to use PL PCIE in the PCIe edge connectors, then any PL reset pin can be used.
After the reset is released, the core attempts to link train and resumes normal operation.
The DMA subsystem receives the reset signal user_reset from the PL PCIE. The DMA subsystem uses user_reset as main reset for all its logic. When the PL PCIE goes through
a reset or there is a link down, it issues a user_reset
to the DMA subsystem. After the PCIe link is up, the user_reset is released for the DMA subsystem.