PCIe MISC Tab - 1.0 English - PG344

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2022-05-20
Version
1.0 English

The PCIe Miscellaneous tab options for the AXI Bridge subsystem are shown in the following figure.

Figure 1. PCIe Miscellaneous Tab

The options are defined as follows:

Legacy Interrupt Settings
Select one of the Legacy Interrupts: INTA, INTB, INTC, or INTD.
MSI-X Capabilities
MSI-X is enabled by default.
The MSI-X settings for different physical functions can be set as required.
section can be done for all select PF's.
MSI-X Table Settings
Defines the MSI-X Table Structure.
Table Size
Specifies the MSI-X Table size. The default is 8 (8 interrupt vectors per function). Adding more vectors to a function is possible; contact Xilinx for support.
Table Offset
Specifies the offset from the Base address Register (BAR) in DMA configuration space used to map function in MSI-X Table onto memory space. MSI-X table space is fixed at offset 0x30000.
PBA table is fixed at offset 0x34000
Access Control Server (ACS) Enable
ACS is selected by default.
Link Status Register
By default, Enable Slot Clock Configuration is selected. This means that the slot configuration bit is enabled in the link status register.