The AXI Bridge Subsystem is designed for the Vivado® IP integrator in the Vivado® Design Suite. The AXI Bridge Subsystem provides an interface between an AXI4 user logic interface and PCI Express® using the Versal® Integrated Block for PCI Express. The AXI Bridge subsystem provides the translation level between the AXI4 embedded system to the PCI Express system. The AXI Bridge subsystem translates the AXI4 memory read or writes to PCI™ Transaction Layer Packets (TLP) packets and translates PCIe memory read and write request TLP packets to AXI4 interface commands.
The architecture of the AXI Bridge is shown in the following figure.