Asserting one or more bits of usr_irq_req causes
the generation of an MSI-X interrupt if MSI-X is enabled. If both MSI-X capabilities are
enabled, an MSI-X interrupt is generated. The MSI-X interrupts mode is enabled when you
set the MSI-X Implementation Location option to Internal in the PCIe Misc Tab.
After a usr_irq_req bit is asserted, it must
remain asserted until the corresponding usr_irq_ack bit
is asserted and the interrupt has been serviced and cleared by the Host. The usr_irq_ack assertion indicates the requested interrupt has
been sent on the PCIe block. This will ensure the
interrupt pending register within the IP remains asserted when queried by the Host's
Interrupt Service Routine (ISR) to determine the source of interrupts. You must
implement a mechanism in the user application to know when the interrupt routine has
been serviced. This detection can be done in many different ways depending on your
application and your use of this interrupt pin. This typically involves a register (or
array of registers) implemented in the user application that is cleared, read, or
modified by the Host software when an Interrupt is serviced.
Configuration registers are available to map usr_irq_req and DMA interrupts to MSI-X vectors. The clock signal (Clock) is
axi_clk.
For
MSI-X support, there is also a vector table and PBA table.
This figure shows only the handshake between usr_irq_req and usr_irq_ack. Your
application might not clear or service the interrupt immediately, in which case, you
must keep usr_irq_req asserted past usr_irq_ack.