The Basic tab is shown in the following figure.
Figure 1. Basic Tab
- Functional Mode
- Option to select between QDMA and AXI Bridge.
- Mode
- Allows you to select the Basic or Advanced mode of the configuration of core.
- Device /Port Type
- Only PCI Express® Endpoint device mode is supported.
- GT Selection/Enable GT Quad Selection
- Select the Quad in which lane 0 is located.
- Lane Width
- The core requires the selection of the initial lane width. The Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343) defines the available widths and associated generated core. Wider lane width cores can train down to smaller lane widths if attached to a smaller lane-width device. Options are 4, 8, or 16 lanes.
- Maximum Link Speed
- The core allows you to select the Maximum Link Speed supported by the device. The Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343) defines the lane widths and link speeds supported by the device. Higher link speed cores are capable of training to a lower link speed if connected to a lower link speed capable device. The default option is Gen3.
- Reference Clock Frequency
- The default is 100 MHz.
- Reset Source
- You can choose one of:
- PCIe User Reset
- The user reset comes from PCIe core after the link is established. When the PCIe link goes down, the user reset is asserted and the core goes to reset mode. And when the link comes back up, the user reset is deasserted.
- Phy Ready
- When selected, the core is not affected by PCIe link status.
- AXI Data Width
- Select 128, 256 bit, or 512 bit. The core allows you to select the Interface Width, as defined in the Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343). The default interface width set in the Customize IP dialog box is the lowest possible interface width.
- AXI Clock Frequency
- 250 MHz depending on the lane width/speed.
- DMA Interface Option
- You can select one of these options:
- AXI Memory Mapped and AXI Stream with Completion
- AXI Memory Mapped only
- AXI Stream with Completion
- Number of Queues (up to 2048)
- Selects maximum number of queues. Options are 512 (default), 1024 and 2048.
- Enable Bridge Slave Mode
- Select to enable the AXI-MM Slave interface.
- VDM Enable
- Select to enable Vendor Define Messages.
- AXI Lite Slave Interface
- Select to enable the AXI4-Lite slave interface, which can access DMA queue space.
- AXI Lite CSR Slave Interface
- Select to enable the AXI4-Lite CSR slave interface, which can access DMA Configuration Space Register or Bridge registers.
- Enable PIPE Simulation
- When selected, this option enables an external third-party bus functional model (BFM) to connect to the PIPE interface of integrated block for PCIe. For details, see PIPE Mode Simulation Using Integrated Endpoint PCI Express Block in Gen3 x8 and Gen2 x8 Configurations (XAPP1184). Refer to these designs to connect the External PIPE Interface ports of the Versal® ACAP core to third-party BFMs.
- Tandem Configuration or Dynamic Function eXchange
- There is no dedicated support for Tandem Configuration or Dynamic Function eXchange using the PL-based PCIe hard block.