Protocol Description - 1.0 English

This section describes the operation of the Soft ECC Proxy LogiCORE™ IP core.

Figure 1. Core Write Ports

Figure 2. Core Read Ports

The Soft ECC Proxy LogiCORE IP uses the industry standard AMBA AXI4 Protocol Specification.

AXI register Slice: The handshake mechanism from slave AXI to Master AXI is implemented with Register Slice for each channel.
Address Converter: The ECC value is calculated for every byte of input data separately and placed along with data bits. Each data byte concatenated with its calculated check bits (8-bits) (check bits are in MSB) and become 16-bits. Thus, N-bytes of data becomes 2N-bytes after encoding. The AXI4 address is byte addressable. The address value and address width can be converted to handle the doubling of data width after encoding. Ex: Address value 0x40 on slave AXI interface converted to 0x80 on master AXI interface for the same data byte.
Error Injection: The Soft ECC Proxy LogiCORE IP supports error injection feature and it can be enabled using C_EN_ERROR_INJECT parameter. When this feature in enabled, a single/double bit error is injected on to every byte of write data after encoding if the corresponding input signal(inject_sbiterr/dbiterr) is high. If both the input signals are high, then double bit error is injected.
Note: Note: One single bit error is injected for every 16bits of data after encoding. One double bit error is injected for every 16bits of data after encoding(one on actual data byte and one on ecc byte). The position of the error changes randomly.
Read Outstanding: The Soft ECC Proxy LogiCORE IP supports read outstanding feature and it can be enabled using C_OUTSTANDING_SUPPORT_RD parameter. This parameter ranges from 1 to 64. The value of 1 means read outstanding is not supported. The value of greater than 1 means read outstanding is supported. It means these many number of read transactions can be stored in the Read address channel AXI register slice when the master is not ready to accept the read transactions.

The following figures detail the AXI4 Write burst transaction and the AXI4 Read burst transaction respectively.

Figure 3. AXI4 Write Burst Transaction

From the figure:

AW_CMD_SLAVE: Write Address command signals on slave interface other than awaddr, awsize, awvalid, and awready.
W_CMD_SLAVE: Write Data interface signals on slave interface other than wdata, wstrb, wvalid, and wready.
B_CMD_SLAVE: Write Response channel signals on slave interface other than bvalid and bready.
AW_CMD_MASTER: Write Burst Write Address command signals on master interface other than awaddr, awsize, awvalid, and awready; .
W_CMD_MASTER: Write Data interface signals on master interface other than wdata, wstrb, wvalid, and wready.
B_CMD_MASTER: Write Response channel signals on master interface other than bvalid and bready.

Figure 4. AXI4 Read Burst Transaction

From the figure:

AR_CMD_SLAVE: Read Address command signals on slave interface other than araddr, arsize, arvalid, and arready.
R_CMD_SLAVE: Read Data interface signals on slave interface other than rdata, rvalid, and rready.
AR_CMD_MASTER: Read Address command signals on master interface other than araddr, arsize, arvalid, and arready.
R_CMD_MASTER: Read Data interface signals on master interface other than rdata, rvalid, and rready.