Interface Ports - 1.0 English

Table 1. Interface Ports
Port Name	I/O	Width	Description
s_aclk	Input	1	Global Slave Interface Clock: All signals are sampled on the rising edge of this clock.
s_aresetn	Input	1	Active-Low Asynchronous Reset
AXI4-Lite Interface
s_axil_awaddr	Input	32	AXI4-Lite Write Address
s_axil_awprot	Input	3	AXI4-Lite Write Protection Type
s_axil_awvalid	Input	1	AXI4-Lite Write Address Valid
s_axil_awready	Output	1	AXI4-Lite Write Address Ready
s_axil_wdata	Input	32	AXI4-Lite Write Data
s_axil_wstrb	Input	4	AXI4-Lite Write Strobe
s_axil_wvalid	Input	1	AXI4-Lite Write Data Valid
s_axil_wready	Output	1	AXI4-Lite Write Data Ready
s_axil_bresp	Output	2	AXI4-Lite Write Response
s_axil_bvalid	Output	1	AXI4-Lite Write Response Valid
s_axil_bready	Input	1	AXI4-Lite Write Response Ready
s_axil_araddr	Input	32	AXI4-Lite Read Address
s_axil_arprot	Input	3	AXI4-Lite Read Protection Type
s_axil_arvalid	Input	1	AXI4-Lite Read Address Valid
s_axil_arready	Output	1	AXI4-Lite Read Address Ready
s_axil_rdata	Output	32	AXI4-Lite Read Data
s_axil_rresp	Output	2	AXI4-Lite Read Response
s_axil_rvalid	Output	1	AXI4-Lite Read Data Valid
s_axil_rready	Input	1	AXI4-Lite Read Data Ready
AXI4-Lite - MM Slave Interface (Write Address Channel)
s_axi_awid	Input	C_ID_WIDTH	Write Address ID: Identification tag for the write address group of signals.
s_axi_awaddr	Input	C_ADDR_WIDTH	Write Address: The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
s_axi_awlen	Input	8	Burst Length: The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
s_axi_awsize	Input	3	Burst Size: Indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
s_axi_awburst	Input	2	Burst Type: The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
s_axi_awlock	Input	2	Lock Type: This signal provides additional information about the atomic characteristics of the transfer.
s_axi_awcache	Input	4	Cache Type: Indicates the buffer-able, cache-able, write-through, write-back, and allocate attributes of the transaction.
s_axi_awprot	Input	3	Protection Type: Indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
s_axi_awqos	Input	4	Quality of Service (QoS): Sent on the write address channel for each write transaction.
s_axi_awregion	Input	4	Region Identifier: Sent on the write address channel for each write transaction.
s_axi_awuser	Input	C_AWUSER_WIDTH	Write Address Channel User
s_axi_awvalid	Input	1	Write Address Valid: Indicates that valid write address and control information are available.
s_axi_awready	Output	1	Write Address Ready: Indicates that the slave is ready to accept an address and associated control signals.
AXI4-Lite - MM Slave Interface (Write Data Channel)
s_axi_wdata	Input	C_DATA_WIDTH	Write Data: The write data bus can be 8, 16, 32, 64, 128, 256, or 512 bits wide.
s_axi_wstrb	Input	C_DATA_WIDTH/8	Write Strobes: Indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
s_axi_wlast	Input	1	Write Last: Indicates the last transfer in a write burst.
s_axi_wuser	Input	C_WUSER_WIDTH	Write Data Channel User
s_axi_wvalid	Input	1	Write Valid: Indicates that valid write data and strobes are available.
s_axi_wready	Output	1	Write Ready: Indicates that the slave can accept the write data.
AXI4-Lite - MM Slave Interface (Write Response Channel)
s_axi_bid	Output	C_ID_WIDTH	Response ID: The identification tag of the write response. The BID value must match the AWID value of the write transaction to which the slave is responding.
s_axi_bresp	Output	2	Write Response: Indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
s_axi_buser	Output	C_BUSER_WIDTH	Write Response Channel User
s_axi_bvalid	Output	1	Write Response Valid: Indicates that a valid write response is available.
s_axi_bready	Input	1	Response Ready: Indicates that the master can accept the response information.
AXI4-Lite - MM Slave Interface (Read Address Channel)
s_axi_arid	Input	C_ID_WIDTH	Read Address ID: This signal is the identification tag for the read address group of signals.
s_axi_araddr	Input	C_ADDR_WIDTH	Read Address: The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is provided and the control signals that are issued alongside the address detail how the address is calculated for the remaining transfers in the burst.
s_axi_arlen	Input	8	Burst Length: The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
s_axi_arsize	Input	3	Burst Size: This signal indicates the size of each transfer in the burst.
s_axi_arburst	Input	2	Burst Type: The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
s_axi_arlock	Input	2	Lock Type: This signal provides additional information about the atomic characteristics of the transfer.
s_axi_arcache	Input	4	Cache Type: This signal provides additional information about the cache-able characteristics of the transfer.
s_axi_arprot	Input	3	Protection Type: This signal provides protection unit information for the transaction.
s_axi_arqos	Input	4	Quality of Service (QoS): Sent on the read address channel for each read transaction.
s_axi_arregion	Input	4	Region Identifier: Sent on the read address channel for each read transaction.
s_axi_aruser	Input	C_ARUSER_WIDTH	Read Address Channel User
s_axi_arvalid	Input	1	Read Address Valid: When High, indicates that the read address and control information is valid and will remain stable until the address acknowledge signal, `arready` is high.
s_axi_arready	Output	1	Read Address Ready: Indicates that the slave is ready to accept an address and associated control signals.
AXI4-Lite - MM Slave Interface (Read Data Channel)
s_axi_rid	Output	C_ID_WIDTH	Read ID Tag: ID tag of the read data group of signals. The RID value is generated by the slave and must match the ARID value of the read transaction to which it is responding.
s_axi_rdata	Output	C_DATA_WIDTH	Read Data: Can be 8, 16, 32, 64, 128, 256, or 512 bits wide.
s_axi_rresp	Output	2	Read Response: Indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
s_axi_rlast	Output	1	Read Last: Indicates the last transfer in a read burst.
s_axi_ruser	Output	C_RUSER_WIDTH	Read Data Channel User
s_axi_rvalid	Output	1	Read Valid: Indicates that the required read data is available and the read transfer can complete.
s_axi_rready	Input	1	Read Ready: Indicates that the master can accept the read data and response information.
AXI4-Lite - MM Master Interface (Write Address Channel)
m_axi_awid	Output	C_ID_WIDTH	Write Address ID: Identification tag for the write address group of signals.
m_axi_awaddr	Output	C_ADDR_WIDTH+1	Write Address: The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
m_axi_awlen	Output	8	Burst Length: The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
m_axi_awsize	Output	3	Burst Size: Indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
m_axi_awburst	Output	2	Burst Type: The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
m_axi_awlock	Output	2	Lock Type: This signal provides additional information about the atomic characteristics of the transfer.
m_axi_awcache	Output	4	Cache Type: Indicates the buffer-able, cache-able, write-through, write-back, and allocate attributes of the transaction.
m_axi_awprot	Output	3	Protection Type: Indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
m_axi_awqos	Output	4	Quality of Service (QoS): Sent on the write address channel for each write transaction.
m_axi_awregion	Output	4	Region Identifier: Sent on the write address channel for each write transaction.
m_axi_awuser	Output	C_AWUSER_WIDTH	Write Address Channel User
m_axi_awvalid	Output	1	Write Address Valid: Indicates that valid write address and control information are available.
m_axi_awready	Input	1	Write Address Ready: Indicates that the slave is ready to accept an address and associated control signals.
AXI4-Lite - MM Slave Interface (Write Data Channel)
m_axi_wdata	Output	2*C_DATA_WIDTH	Write Data: The write data bus can be 8, 16, 32, 64, 128, 256, or 512 bits wide.
m_axi_wstrb	Output	2*C_DATA_WIDTH/8	Write Strobes: Indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
m_axi_wlast	Output	1	Write Last: Indicates the last transfer in a write burst.
m_axi_wuser	Output	C_WUSER_WIDTH	Write Data Channel User
m_axi_wvalid	Output	1	Write Valid: Indicates that valid write data and strobes are available.
m_axi_wready	Input	1	Write Ready: Indicates that the slave can accept the write data.
AXI4-Lite - MM Slave Interface (Write Response Channel)
m_axi_bid	Input	C_ID_WIDTH	Response ID: The identification tag of the write response. The BID value must match the AWID value of the write transaction to which the slave is responding.
m_axi_bresp	Input	2	Write Response: Indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
m_axi_buser	Input	C_BUSER_WIDTH	Write Response Channel User
m_axi_bvalid	Input	1	Write Response Valid: Indicates that a valid write response is available.
m_axi_bready	Output	1	Response Ready: Indicates that the master can accept the response information.
AXI4-Lite - MM Slave Interface (Read Address Channel)
m_axi_arid	Output	C_ID_WIDTH	Read Address ID: This signal is the identification tag for the read address group of signals.
m_axi_araddr	Output	C_ADDR_WIDTH+1	Read Address: The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is provided and the control signals that are issued alongside the address detail how the address is calculated for the remaining transfers in the burst.
m_axi_arlen	Output	8	Burst Length: The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
m_axi_arsize	Output	3	Burst Size: This signal indicates the size of each transfer in the burst.
m_axi_arburst	Output	2	Burst Type: The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
m_axi_arlock	Output	2	Lock Type: This signal provides additional information about the atomic characteristics of the transfer.
m_axi_arcache	Output	4	Cache Type: This signal provides additional information about the cache-able characteristics of the transfer.
m_axi_arprot	Output	3	Protection Type: This signal provides protection unit information for the transaction.
m_axi_arqos	Output	4	Quality of Service (QoS): Sent on the read address channel for each read transaction.
m_axi_arregion	Output	4	Region Identifier: Sent on the read address channel for each read transaction.
m_axi_aruser	Output	C_ARUSER_WIDTH	Read Address Channel User
m_axi_arvalid	Output	1	Read Address Valid: When High, indicates that the read address and control information is valid and will remain stable until the address acknowledge signal, `arready` is high.
m_axi_arready	Input	1	Read Address Ready: Indicates that the slave is ready to accept an address and associated control signals.
AXI4-Lite - MM Slave Interface (Read Data Channel)
m_axi_rid	Input	C_ID_WIDTH	Read ID Tag: ID tag of the read data group of signals. The RID value is generated by the slave and must match the ARID value of the read transaction to which it is responding.
m_axi_rdata	Input	2*C_DATA_WIDTH	Read Data: Can be 8, 16, 32, 64, 128, 256, or 512 bits wide.
m_axi_rresp	Input	2	Read Response: Indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
m_axi_rlast	Input	1	Read Last: Indicates the last transfer in a read burst.
m_axi_ruser	Input	C_RUSER_WIDTH	Read Data Channel User
m_axi_rvalid	Input	1	Read Valid: Indicates that the required read data is available and the read transfer can complete.
m_axi_rready	Output	1	Read Ready: Indicates that the master can accept the read data and response information.
Error Inject Signals
inject_sbiterr	Input	1	Inject Single-Bit Error
inject_dbiterr	Input	1	Inject Double-Bit Error
Interrupts
ecc_interrupt	Output	1	ECC Interrupt: Indicates single/double bit error occurred on read data path