The Soft ECC Proxy IP core operates on a single clock (s_aclk), and all input and output interface signals of the
AXI4-Lite and AXI4 Master/Slave interfaces are synchronized with this clock.
The Soft ECC Proxy IP core operates on a single clock (s_aclk), and all input and output interface signals of the
AXI4-Lite and AXI4 Master/Slave interfaces are synchronized with this clock.