Raw Throughput Evaluation - 1.0 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)
Document ID
PG313
Release Date
2023-11-01
Version
1.0 English
It is important to understand the raw throughput of the HBM stacks and how the user logic must be designed to match this data rate. Each HBM stack has eight channels, each channel has a dedicated controller, each controller is operating in pseudo channel mode, each pseudo channel is 64 bits wide, and the data bits toggle at twice the HBM clock rate set in the IP configuration. If the HBM IP is configured with a 1600 MHz clock rate, the toggle rate for a single HBM stack can be evaluated using the following formula:

  • (64 bits per pseudo channel) x (2 pseudo channels per memory controller) x (8 channels) x 1600 MHz x 2

This results in 3,276,800 Mb per second per stack, or 409,600 MB per second per stack. Double this value to 819,200 MB per second for a dual stack device.

Each pseudo channel provides up to 25.6 GB/s of bandwidth using the following equation:

  • (64 bits on each pseudo channel) x 1600 MHz x 2

From the user logic perspective, the maximum throughput of each physical link through the NoC is limited to 17.28 GB/s for reads and somewhat less for writes. Therefore, it is necessary in some cases to use both ports of each pseudo channel to achieve the maximum available bandwidth. Refer to Physical Link (Raw) Bandwidth to understand more about this.

There are 32 HBM_NMUs providing direct access to an HBM stack, with each port being 256 bits wide. HBM bandwidth saturates when HBM_NMUs operate at 400 MHz. Each port has access to the entire HBM stack volume via the HNoC. The throughput of all the HBM_NMU ports is calculated using the following formula:

  • (256 bits per HBM_NMU port) x (32 HBM_NMU ports) x 400 MHz

This results in 409,600 MB/s per stack and 819,200 MB/s for two stacks.