This training finds the correct cycle to
maintain the set Write Latency value in the DRAM. In this training mode, the controller
pre-programs the data buffer MPR registers with the expected pattern, issues write
commands to load the data into memory, and issues reads to the memory. The data buffer
compares the read data with the expected data and feeds back the result on to the DQ
bus. Calibration identifies the correct cycle based on the result of the comparison.
Table 1. MWD Cycle Training Register
Register Name |
Quantity |
Description |
Fx_DB_DWL_MWD_LAT |
Rank |
Data Buffer to DRAM latency [8:6] and Data
Buffer phase [5:0] |