After the DQS gate multi-rank adjustment (if required), a signal is sent to the XPHY to recalibrate internal delays and to start voltage and temperature tracking.
For multi-rank systems, when all nibbles are ready for normal operation the XPHY
requires two write-read bursts to be sent to the DRAM before starting normal traffic. A
data pattern of F00FF00F is used for the first and
0FF00FF0 for the second. The data itself is not
checked and is expected to fail.