The DDRMC can also be configured as two independent DDR interfaces of 16, 24, or 32 data bits each. The flipped 2x component pinout configurations are included in this section.
Nibble utilization for 2x32 interface using SDP, DDP (2 Ranks) or 3DS components in the flipped configuration is shown in the following figure. DQL and DQR indicate data nibbles for the left and right interfaces respectively, ACL and ACR indicate Address/Command/Control nibbles for the left and right interfaces respectively, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. For a 1x32 interface all nibbles in the second Bank and nibbles 0, 1, 4, and 5 in the first Bank would be free.
Nibble utilization for 2x16 interface using SDP, DDP (2 Ranks) or
3DS components in the flipped configuration is shown in the following figure. DQL
and DQR indicate data nibbles for the left and right interfaces respectively, ACL
and ACR indicate Address/Command/Control nibbles for the left and right interfaces
respectively, sys_clk
indicates a nibble
comprising the System Clock pair, RESET_n, and ALERT_n signals. For a 1x16 interface
all nibbles in the second Bank would be free Bank in addition to the free nibbles in
the first Bank.
Nibble utilization for 2x24 interface using SDP, DDP (2 Ranks) or 3DS components in the flipped configuration is shown in the following figure. DQL and DQR indicate data nibbles for the left and right interfaces respectively, ACL and ACR indicate Address/Command/Control nibbles for the left and right interfaces respectively, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. For a 1x24 interface all nibbles in the second Bank would be free and nibbles 4 and 5 in addition to nibbles 0, 1, 2, and 3 in the first Bank would be free.