• Review Versal™ product and system architecture​
• Select target device​
• Identify performance requirements​
• Identify power requirements​
• Identify memory requirements
• Identify I/O requirements​
• Review and select PCI Express® and Ethernet protocols​
• Identify additional design requirements

• Create Vivado Project
• Create a block design with CIPS, NoC/DDRMC, GT using Vivado IP Integrator
• Configure CIPS for PMC-based boot modes, SYSMON, SEM, readback V*
• Apply NoC performance constraints V*
• Apply I/O placement constraints
• Design IP in RTL or C/C++ using HLS
• Ensure design adheres to coding guidelines
• Constrain the block level design, run methodology checks, and validate performance
• Assemble top-level design, complete constraints, and run methodology checks

V* = New and required for Versal designs

• Evaluate device capabilites
• Perform schematic entry
• Lay out and simulate the board design
• Prototype, build, and test

• Simulate the design for functionality and early performance assessment
• Iterate on design timing and power closure
• Generate programmable device image (includes PLM firmware) V*
• Perform hardware functional testing
• Validate performance in hardware

V* = New and required for Versal designs