MEMORY_TILE_MODULE Module

MEMORY_TILE_MODULE Module Description

Module Type	MEMORY_TILE_MODULE Module
Base Addresses	The register base addresses for memory tile modules can be found by using the following formula: Register Base Address = 0x200_0000_0000 + (<colnum> * 32 + <rownum + 1>) * 0x10_0000 Note: The first row of memory tiles is rownum 0. For the calculated addresses for each device, see Answer Record 000036946.
Description	Memory Tile Control and Status Registers

Module Type

Base Addresses

The register base addresses for memory tile modules can be found by using the following formula:
Register Base Address = 0x200_0000_0000 + (<colnum> * 32 + <rownum + 1>) * 0x10_0000
Note: The first row of memory tiles is rownum 0.

For the calculated addresses for each device, see Answer Record 000036946.

Description

Memory Tile Control and Status Registers

MEMORY_TILE_MODULE Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
DataMemory	0x0000000000	128	rwNormal read/write	0x00000000	DataMemory of 16 banks, 128-bit wide, 512kB
Performance_Control0	0x0000091000	32	rwNormal read/write	0x00000000	Performance Counters 1-0 Start and Stop Event
Performance_Control1	0x0000091004	32	rwNormal read/write	0x00000000	Performance Counters 3-2 Start and Stop Event
Performance_Control2	0x0000091008	32	rwNormal read/write	0x00000000	Performance Counters Reset Event
Performance_Counter0	0x0000091020	32	rwNormal read/write	0x00000000	Performance Counter0
Performance_Counter1	0x0000091024	32	rwNormal read/write	0x00000000	Performance Counter1
Performance_Counter2	0x0000091028	32	rwNormal read/write	0x00000000	Performance Counter2
Performance_Counter3	0x000009102C	32	rwNormal read/write	0x00000000	Performance Counter3
Performance_Counter0_Event_Value	0x0000091080	32	rwNormal read/write	0x00000000	Performance Counter0 Event Value.
Performance_Counter1_Event_Value	0x0000091084	32	rwNormal read/write	0x00000000	Performance Counter1 Event Value.
Performance_Counter2_Event_Value	0x0000091088	32	rwNormal read/write	0x00000000	Performance Counter2 Event Value.
Performance_Counter3_Event_Value	0x000009108C	32	rwNormal read/write	0x00000000	Performance Counter3 Event Value.
Timer_Control	0x0000094000	32	mixedMixed types. See bit-field details.	0x00000000	Control of Internal Timer
Event_Generate	0x0000094008	32	woWrite-only	0x00000000	Generate an internal event
Event_Broadcast0	0x0000094010	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast0
Event_Broadcast1	0x0000094014	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast1
Event_Broadcast2	0x0000094018	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast2
Event_Broadcast3	0x000009401C	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast3
Event_Broadcast4	0x0000094020	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast4
Event_Broadcast5	0x0000094024	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast5
Event_Broadcast6	0x0000094028	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast6
Event_Broadcast7	0x000009402C	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast7
Event_Broadcast8	0x0000094030	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast8
Event_Broadcast9	0x0000094034	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast9
Event_Broadcast10	0x0000094038	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast10
Event_Broadcast11	0x000009403C	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast11
Event_Broadcast12	0x0000094040	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast12
Event_Broadcast13	0x0000094044	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast13
Event_Broadcast14	0x0000094048	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast14
Event_Broadcast15	0x000009404C	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast15
Event_Broadcast_A_Block_South_Set	0x0000094050	32	woWrite-only	0x00000000	Set block of broadcast signals to South
Event_Broadcast_A_Block_South_Clr	0x0000094054	32	woWrite-only	0x00000000	Clear block of broadcast signals to South
Event_Broadcast_A_Block_South_Value	0x0000094058	32	roRead-only	0x00000000	Current value of block for broadcast signals to South
Event_Broadcast_A_Block_West_Set	0x0000094060	32	woWrite-only	0x00000000	Set block of broadcast switch A signals to West
Event_Broadcast_A_Block_West_Clr	0x0000094064	32	woWrite-only	0x00000000	Clear block of broadcast switch A signals to West
Event_Broadcast_A_Block_West_Value	0x0000094068	32	roRead-only	0x00000000	Current value of block for broadcast switch A signals to West
Event_Broadcast_A_Block_North_Set	0x0000094070	32	woWrite-only	0x00000000	Set block of broadcast switch A signals to North
Event_Broadcast_A_Block_North_Clr	0x0000094074	32	woWrite-only	0x00000000	Clear block of broadcast switch A signals to North
Event_Broadcast_A_Block_North_Value	0x0000094078	32	roRead-only	0x00000000	Current value of block for broadcast switch A signals to North
Event_Broadcast_A_Block_East_Set	0x0000094080	32	woWrite-only	0x00000000	Set block of broadcast switch A signals to East
Event_Broadcast_A_Block_East_Clr	0x0000094084	32	woWrite-only	0x00000000	Clear block of broadcast switch A signals to East
Event_Broadcast_A_Block_East_Value	0x0000094088	32	roRead-only	0x00000000	Current value of block for broadcast switch A signals to East
Event_Broadcast_B_Block_South_Set	0x0000094090	32	woWrite-only	0x00000000	Set block of broadcast switch B signals to South
Event_Broadcast_B_Block_South_Clr	0x0000094094	32	woWrite-only	0x00000000	Clear block of broadcast switch B signals to South
Event_Broadcast_B_Block_South_Value	0x0000094098	32	roRead-only	0x00000000	Current value of block for broadcast switch B signals to South
Event_Broadcast_B_Block_West_Set	0x00000940A0	32	woWrite-only	0x00000000	Set block of broadcast switch B signals to West
Event_Broadcast_B_Block_West_Clr	0x00000940A4	32	woWrite-only	0x00000000	Clear block of broadcast switch B signals to West
Event_Broadcast_B_Block_West_Value	0x00000940A8	32	roRead-only	0x00000000	Current value of block for broadcast switch B signals to West
Event_Broadcast_B_Block_North_Set	0x00000940B0	32	woWrite-only	0x00000000	Set block of broadcast switch B signals to North
Event_Broadcast_B_Block_North_Clr	0x00000940B4	32	woWrite-only	0x00000000	Clear block of broadcast switch B signals to North
Event_Broadcast_B_Block_North_Value	0x00000940B8	32	roRead-only	0x00000000	Current value of block for broadcast switch B signals to North
Event_Broadcast_B_Block_East_Set	0x00000940C0	32	woWrite-only	0x00000000	Set block of broadcast switch B signals to East
Event_Broadcast_B_Block_East_Clr	0x00000940C4	32	woWrite-only	0x00000000	Clear block of broadcast switch B signals to East
Event_Broadcast_B_Block_East_Value	0x00000940C8	32	roRead-only	0x00000000	Current value of block for broadcast switch B signals to East
Trace_Control0	0x00000940D0	32	rwNormal read/write	0x00000000	Control of Trace
Trace_Control1	0x00000940D4	32	rwNormal read/write	0x00000000	Control of Trace: packet configuration
Trace_Status	0x00000940D8	32	roRead-only	0x00000000	Status of trace engine
Trace_Event0	0x00000940E0	32	rwNormal read/write	0x00000000	Control of which Internal Event to Trace
Trace_Event1	0x00000940E4	32	rwNormal read/write	0x00000000	Control of which Internal Event to Trace
Timer_Trig_Event_Low_Value	0x00000940F0	32	rwNormal read/write	0xFFFFFFFF	Internal Timer Event Value.
Timer_Trig_Event_High_Value	0x00000940F4	32	rwNormal read/write	0xFFFFFFFF	Internal Timer Event Value.
Timer_Low	0x00000940F8	32	roRead-only	0x00000000	Internal Timer Low part Value.
Timer_High	0x00000940FC	32	roRead-only	0x00000000	Internal Timer High part Value.
WatchPoint0	0x0000094100	32	rwNormal read/write	0x00000000	Define Watchpoint0
WatchPoint1	0x0000094104	32	rwNormal read/write	0x00000000	Define Watchpoint1
WatchPoint2	0x0000094108	32	rwNormal read/write	0x00000000	Define Watchpoint2
WatchPoint3	0x000009410C	32	rwNormal read/write	0x00000000	Define Watchpoint3
Event_Status0	0x0000094200	32	wtcReadable, write a 1 to clear	0x00000002	Internal event status register0
Event_Status1	0x0000094204	32	wtcReadable, write a 1 to clear	0x00000000	Internal event status register1
Event_Status2	0x0000094208	32	wtcReadable, write a 1 to clear	0x00000000	Internal event status register2
Event_Status3	0x000009420C	32	wtcReadable, write a 1 to clear	0x00000000	Internal event status register3
Event_Status4	0x0000094210	32	wtcReadable, write a 1 to clear	0x00000000	Internal event status register4
Event_Status5	0x0000094214	32	wtcReadable, write a 1 to clear	0x00000000	Internal event status register5
Combo_event_inputs	0x0000094400	32	rwNormal read/write	0x00000000	Combo events input events
Combo_event_control	0x0000094404	32	rwNormal read/write	0x00000000	Combo events input events
Edge_Detection_event_control	0x0000094408	32	rwNormal read/write	0x00000000	Configuration for edge detection events
Event_Group_0_Enable	0x0000094500	32	rwNormal read/write	0x00000FFF	Event enable for Group 0
Event_Group_Watchpoint_Enable	0x0000094504	32	rwNormal read/write	0x0000000F	Event enable for Watchpoint Group
Event_Group_DMA_Enable	0x0000094508	32	rwNormal read/write	0x00FFFFFF	Event enable for DMA Group
Event_Group_Lock_Enable	0x000009450C	32	rwNormal read/write	0xFFFFFFFF	Event enable for Lock Group
Event_Group_Stream_Switch_Enable	0x0000094510	32	rwNormal read/write	0xFFFFFFFF	Event enable for Stream Switch Group
Event_Group_Memory_Conflict_Enable	0x0000094514	32	rwNormal read/write	0x0000FFFF	Event enable for Memory Conflict Group
Event_Group_Error_Enable	0x0000094518	32	rwNormal read/write	0x00000FFF	Event enable for Error Group
Event_Group_Broadcast_Enable	0x000009451C	32	rwNormal read/write	0x0000FFFF	Event enable for Broadcast Group
Event_Group_User_Event_Enable	0x0000094520	32	rwNormal read/write	0x00000003	Event enable for User Group
Tile_Control	0x0000096030	32	rwNormal read/write	0x0000000F	Tile control register
Memory_Control	0x0000096048	32	rwNormal read/write	0x00000002	Control for memory (privileged)
DMA_BD0_0	0x00000A0000	32	rwNormal read/write	0x00000000	DMA BD0 0
DMA_BD0_1	0x00000A0004	32	rwNormal read/write	0x00000000	DMA BD0 1
DMA_BD0_2	0x00000A0008	32	rwNormal read/write	0x00000000	DMA BD0 2
DMA_BD0_3	0x00000A000C	32	rwNormal read/write	0x00000000	DMA BD0 3
DMA_BD0_4	0x00000A0010	32	rwNormal read/write	0x00000000	DMA BD0 4
DMA_BD0_5	0x00000A0014	32	rwNormal read/write	0x00000000	DMA BD0 5
DMA_BD0_6	0x00000A0018	32	rwNormal read/write	0x00000000	DMA BD0 6
DMA_BD0_7	0x00000A001C	32	rwNormal read/write	0x00000000	DMA BD0 7
DMA_BD1_0	0x00000A0020	32	rwNormal read/write	0x00000000	DMA BD1 0
DMA_BD1_1	0x00000A0024	32	rwNormal read/write	0x00000000	DMA BD1 1
DMA_BD1_2	0x00000A0028	32	rwNormal read/write	0x00000000	DMA BD1 2
DMA_BD1_3	0x00000A002C	32	rwNormal read/write	0x00000000	DMA BD1 3
DMA_BD1_4	0x00000A0030	32	rwNormal read/write	0x00000000	DMA BD1 4
DMA_BD1_5	0x00000A0034	32	rwNormal read/write	0x00000000	DMA BD1 5
DMA_BD1_6	0x00000A0038	32	rwNormal read/write	0x00000000	DMA BD1 6
DMA_BD1_7	0x00000A003C	32	rwNormal read/write	0x00000000	DMA BD1 7
DMA_BD2_0	0x00000A0040	32	rwNormal read/write	0x00000000	DMA BD2 0
DMA_BD2_1	0x00000A0044	32	rwNormal read/write	0x00000000	DMA BD2 1
DMA_BD2_2	0x00000A0048	32	rwNormal read/write	0x00000000	DMA BD2 2
DMA_BD2_3	0x00000A004C	32	rwNormal read/write	0x00000000	DMA BD2 3
DMA_BD2_4	0x00000A0050	32	rwNormal read/write	0x00000000	DMA BD2 4
DMA_BD2_5	0x00000A0054	32	rwNormal read/write	0x00000000	DMA BD2 5
DMA_BD2_6	0x00000A0058	32	rwNormal read/write	0x00000000	DMA BD2 6
DMA_BD2_7	0x00000A005C	32	rwNormal read/write	0x00000000	DMA BD2 7
DMA_BD3_0	0x00000A0060	32	rwNormal read/write	0x00000000	DMA BD3 0
DMA_BD3_1	0x00000A0064	32	rwNormal read/write	0x00000000	DMA BD3 1
DMA_BD3_2	0x00000A0068	32	rwNormal read/write	0x00000000	DMA BD3 2
DMA_BD3_3	0x00000A006C	32	rwNormal read/write	0x00000000	DMA BD3 3
DMA_BD3_4	0x00000A0070	32	rwNormal read/write	0x00000000	DMA BD3 4
DMA_BD3_5	0x00000A0074	32	rwNormal read/write	0x00000000	DMA BD3 5
DMA_BD3_6	0x00000A0078	32	rwNormal read/write	0x00000000	DMA BD3 6
DMA_BD3_7	0x00000A007C	32	rwNormal read/write	0x00000000	DMA BD3 7
DMA_BD4_0	0x00000A0080	32	rwNormal read/write	0x00000000	DMA BD4 0
DMA_BD4_1	0x00000A0084	32	rwNormal read/write	0x00000000	DMA BD4 1
DMA_BD4_2	0x00000A0088	32	rwNormal read/write	0x00000000	DMA BD4 2
DMA_BD4_3	0x00000A008C	32	rwNormal read/write	0x00000000	DMA BD4 3
DMA_BD4_4	0x00000A0090	32	rwNormal read/write	0x00000000	DMA BD4 4
DMA_BD4_5	0x00000A0094	32	rwNormal read/write	0x00000000	DMA BD4 5
DMA_BD4_6	0x00000A0098	32	rwNormal read/write	0x00000000	DMA BD4 6
DMA_BD4_7	0x00000A009C	32	rwNormal read/write	0x00000000	DMA BD4 7
DMA_BD5_0	0x00000A00A0	32	rwNormal read/write	0x00000000	DMA BD5 0
DMA_BD5_1	0x00000A00A4	32	rwNormal read/write	0x00000000	DMA BD5 1
DMA_BD5_2	0x00000A00A8	32	rwNormal read/write	0x00000000	DMA BD5 2
DMA_BD5_3	0x00000A00AC	32	rwNormal read/write	0x00000000	DMA BD5 3
DMA_BD5_4	0x00000A00B0	32	rwNormal read/write	0x00000000	DMA BD5 4
DMA_BD5_5	0x00000A00B4	32	rwNormal read/write	0x00000000	DMA BD5 5
DMA_BD5_6	0x00000A00B8	32	rwNormal read/write	0x00000000	DMA BD5 6
DMA_BD5_7	0x00000A00BC	32	rwNormal read/write	0x00000000	DMA BD5 7
DMA_BD6_0	0x00000A00C0	32	rwNormal read/write	0x00000000	DMA BD6 0
DMA_BD6_1	0x00000A00C4	32	rwNormal read/write	0x00000000	DMA BD6 1
DMA_BD6_2	0x00000A00C8	32	rwNormal read/write	0x00000000	DMA BD6 2
DMA_BD6_3	0x00000A00CC	32	rwNormal read/write	0x00000000	DMA BD6 3
DMA_BD6_4	0x00000A00D0	32	rwNormal read/write	0x00000000	DMA BD6 4
DMA_BD6_5	0x00000A00D4	32	rwNormal read/write	0x00000000	DMA BD6 5
DMA_BD6_6	0x00000A00D8	32	rwNormal read/write	0x00000000	DMA BD6 6
DMA_BD6_7	0x00000A00DC	32	rwNormal read/write	0x00000000	DMA BD6 7
DMA_BD7_0	0x00000A00E0	32	rwNormal read/write	0x00000000	DMA BD7 0
DMA_BD7_1	0x00000A00E4	32	rwNormal read/write	0x00000000	DMA BD7 1
DMA_BD7_2	0x00000A00E8	32	rwNormal read/write	0x00000000	DMA BD7 2
DMA_BD7_3	0x00000A00EC	32	rwNormal read/write	0x00000000	DMA BD7 3
DMA_BD7_4	0x00000A00F0	32	rwNormal read/write	0x00000000	DMA BD7 4
DMA_BD7_5	0x00000A00F4	32	rwNormal read/write	0x00000000	DMA BD7 5
DMA_BD7_6	0x00000A00F8	32	rwNormal read/write	0x00000000	DMA BD7 6
DMA_BD7_7	0x00000A00FC	32	rwNormal read/write	0x00000000	DMA BD7 7
DMA_BD8_0	0x00000A0100	32	rwNormal read/write	0x00000000	DMA BD8 0
DMA_BD8_1	0x00000A0104	32	rwNormal read/write	0x00000000	DMA BD8 1
DMA_BD8_2	0x00000A0108	32	rwNormal read/write	0x00000000	DMA BD8 2
DMA_BD8_3	0x00000A010C	32	rwNormal read/write	0x00000000	DMA BD8 3
DMA_BD8_4	0x00000A0110	32	rwNormal read/write	0x00000000	DMA BD8 4
DMA_BD8_5	0x00000A0114	32	rwNormal read/write	0x00000000	DMA BD8 5
DMA_BD8_6	0x00000A0118	32	rwNormal read/write	0x00000000	DMA BD8 6
DMA_BD8_7	0x00000A011C	32	rwNormal read/write	0x00000000	DMA BD8 7
DMA_BD9_0	0x00000A0120	32	rwNormal read/write	0x00000000	DMA BD9 0
DMA_BD9_1	0x00000A0124	32	rwNormal read/write	0x00000000	DMA BD9 1
DMA_BD9_2	0x00000A0128	32	rwNormal read/write	0x00000000	DMA BD9 2
DMA_BD9_3	0x00000A012C	32	rwNormal read/write	0x00000000	DMA BD9 3
DMA_BD9_4	0x00000A0130	32	rwNormal read/write	0x00000000	DMA BD9 4
DMA_BD9_5	0x00000A0134	32	rwNormal read/write	0x00000000	DMA BD9 5
DMA_BD9_6	0x00000A0138	32	rwNormal read/write	0x00000000	DMA BD9 6
DMA_BD9_7	0x00000A013C	32	rwNormal read/write	0x00000000	DMA BD9 7
DMA_BD10_0	0x00000A0140	32	rwNormal read/write	0x00000000	DMA BD10 0
DMA_BD10_1	0x00000A0144	32	rwNormal read/write	0x00000000	DMA BD10 1
DMA_BD10_2	0x00000A0148	32	rwNormal read/write	0x00000000	DMA BD10 2
DMA_BD10_3	0x00000A014C	32	rwNormal read/write	0x00000000	DMA BD10 3
DMA_BD10_4	0x00000A0150	32	rwNormal read/write	0x00000000	DMA BD10 4
DMA_BD10_5	0x00000A0154	32	rwNormal read/write	0x00000000	DMA BD10 5
DMA_BD10_6	0x00000A0158	32	rwNormal read/write	0x00000000	DMA BD10 6
DMA_BD10_7	0x00000A015C	32	rwNormal read/write	0x00000000	DMA BD10 7
DMA_BD11_0	0x00000A0160	32	rwNormal read/write	0x00000000	DMA BD11 0
DMA_BD11_1	0x00000A0164	32	rwNormal read/write	0x00000000	DMA BD11 1
DMA_BD11_2	0x00000A0168	32	rwNormal read/write	0x00000000	DMA BD11 2
DMA_BD11_3	0x00000A016C	32	rwNormal read/write	0x00000000	DMA BD11 3
DMA_BD11_4	0x00000A0170	32	rwNormal read/write	0x00000000	DMA BD11 4
DMA_BD11_5	0x00000A0174	32	rwNormal read/write	0x00000000	DMA BD11 5
DMA_BD11_6	0x00000A0178	32	rwNormal read/write	0x00000000	DMA BD11 6
DMA_BD11_7	0x00000A017C	32	rwNormal read/write	0x00000000	DMA BD11 7
DMA_BD12_0	0x00000A0180	32	rwNormal read/write	0x00000000	DMA BD12 0
DMA_BD12_1	0x00000A0184	32	rwNormal read/write	0x00000000	DMA BD12 1
DMA_BD12_2	0x00000A0188	32	rwNormal read/write	0x00000000	DMA BD12 2
DMA_BD12_3	0x00000A018C	32	rwNormal read/write	0x00000000	DMA BD12 3
DMA_BD12_4	0x00000A0190	32	rwNormal read/write	0x00000000	DMA BD12 4
DMA_BD12_5	0x00000A0194	32	rwNormal read/write	0x00000000	DMA BD12 5
DMA_BD12_6	0x00000A0198	32	rwNormal read/write	0x00000000	DMA BD12 6
DMA_BD12_7	0x00000A019C	32	rwNormal read/write	0x00000000	DMA BD12 7
DMA_BD13_0	0x00000A01A0	32	rwNormal read/write	0x00000000	DMA BD13 0
DMA_BD13_1	0x00000A01A4	32	rwNormal read/write	0x00000000	DMA BD13 1
DMA_BD13_2	0x00000A01A8	32	rwNormal read/write	0x00000000	DMA BD13 2
DMA_BD13_3	0x00000A01AC	32	rwNormal read/write	0x00000000	DMA BD13 3
DMA_BD13_4	0x00000A01B0	32	rwNormal read/write	0x00000000	DMA BD13 4
DMA_BD13_5	0x00000A01B4	32	rwNormal read/write	0x00000000	DMA BD13 5
DMA_BD13_6	0x00000A01B8	32	rwNormal read/write	0x00000000	DMA BD13 6
DMA_BD13_7	0x00000A01BC	32	rwNormal read/write	0x00000000	DMA BD13 7
DMA_BD14_0	0x00000A01C0	32	rwNormal read/write	0x00000000	DMA BD14 0
DMA_BD14_1	0x00000A01C4	32	rwNormal read/write	0x00000000	DMA BD14 1
DMA_BD14_2	0x00000A01C8	32	rwNormal read/write	0x00000000	DMA BD14 2
DMA_BD14_3	0x00000A01CC	32	rwNormal read/write	0x00000000	DMA BD14 3
DMA_BD14_4	0x00000A01D0	32	rwNormal read/write	0x00000000	DMA BD14 4
DMA_BD14_5	0x00000A01D4	32	rwNormal read/write	0x00000000	DMA BD14 5
DMA_BD14_6	0x00000A01D8	32	rwNormal read/write	0x00000000	DMA BD14 6
DMA_BD14_7	0x00000A01DC	32	rwNormal read/write	0x00000000	DMA BD14 7
DMA_BD15_0	0x00000A01E0	32	rwNormal read/write	0x00000000	DMA BD15 0
DMA_BD15_1	0x00000A01E4	32	rwNormal read/write	0x00000000	DMA BD15 1
DMA_BD15_2	0x00000A01E8	32	rwNormal read/write	0x00000000	DMA BD15 2
DMA_BD15_3	0x00000A01EC	32	rwNormal read/write	0x00000000	DMA BD15 3
DMA_BD15_4	0x00000A01F0	32	rwNormal read/write	0x00000000	DMA BD15 4
DMA_BD15_5	0x00000A01F4	32	rwNormal read/write	0x00000000	DMA BD15 5
DMA_BD15_6	0x00000A01F8	32	rwNormal read/write	0x00000000	DMA BD15 6
DMA_BD15_7	0x00000A01FC	32	rwNormal read/write	0x00000000	DMA BD15 7
DMA_BD16_0	0x00000A0200	32	rwNormal read/write	0x00000000	DMA BD16 0
DMA_BD16_1	0x00000A0204	32	rwNormal read/write	0x00000000	DMA BD16 1
DMA_BD16_2	0x00000A0208	32	rwNormal read/write	0x00000000	DMA BD16 2
DMA_BD16_3	0x00000A020C	32	rwNormal read/write	0x00000000	DMA BD16 3
DMA_BD16_4	0x00000A0210	32	rwNormal read/write	0x00000000	DMA BD16 4
DMA_BD16_5	0x00000A0214	32	rwNormal read/write	0x00000000	DMA BD16 5
DMA_BD16_6	0x00000A0218	32	rwNormal read/write	0x00000000	DMA BD16 6
DMA_BD16_7	0x00000A021C	32	rwNormal read/write	0x00000000	DMA BD16 7
DMA_BD17_0	0x00000A0220	32	rwNormal read/write	0x00000000	DMA BD17 0
DMA_BD17_1	0x00000A0224	32	rwNormal read/write	0x00000000	DMA BD17 1
DMA_BD17_2	0x00000A0228	32	rwNormal read/write	0x00000000	DMA BD17 2
DMA_BD17_3	0x00000A022C	32	rwNormal read/write	0x00000000	DMA BD17 3
DMA_BD17_4	0x00000A0230	32	rwNormal read/write	0x00000000	DMA BD17 4
DMA_BD17_5	0x00000A0234	32	rwNormal read/write	0x00000000	DMA BD17 5
DMA_BD17_6	0x00000A0238	32	rwNormal read/write	0x00000000	DMA BD17 6
DMA_BD17_7	0x00000A023C	32	rwNormal read/write	0x00000000	DMA BD17 7
DMA_BD18_0	0x00000A0240	32	rwNormal read/write	0x00000000	DMA BD18 0
DMA_BD18_1	0x00000A0244	32	rwNormal read/write	0x00000000	DMA BD18 1
DMA_BD18_2	0x00000A0248	32	rwNormal read/write	0x00000000	DMA BD18 2
DMA_BD18_3	0x00000A024C	32	rwNormal read/write	0x00000000	DMA BD18 3
DMA_BD18_4	0x00000A0250	32	rwNormal read/write	0x00000000	DMA BD18 4
DMA_BD18_5	0x00000A0254	32	rwNormal read/write	0x00000000	DMA BD18 5
DMA_BD18_6	0x00000A0258	32	rwNormal read/write	0x00000000	DMA BD18 6
DMA_BD18_7	0x00000A025C	32	rwNormal read/write	0x00000000	DMA BD18 7
DMA_BD19_0	0x00000A0260	32	rwNormal read/write	0x00000000	DMA BD19 0
DMA_BD19_1	0x00000A0264	32	rwNormal read/write	0x00000000	DMA BD19 1
DMA_BD19_2	0x00000A0268	32	rwNormal read/write	0x00000000	DMA BD19 2
DMA_BD19_3	0x00000A026C	32	rwNormal read/write	0x00000000	DMA BD19 3
DMA_BD19_4	0x00000A0270	32	rwNormal read/write	0x00000000	DMA BD19 4
DMA_BD19_5	0x00000A0274	32	rwNormal read/write	0x00000000	DMA BD19 5
DMA_BD19_6	0x00000A0278	32	rwNormal read/write	0x00000000	DMA BD19 6
DMA_BD19_7	0x00000A027C	32	rwNormal read/write	0x00000000	DMA BD19 7
DMA_BD20_0	0x00000A0280	32	rwNormal read/write	0x00000000	DMA BD20 0
DMA_BD20_1	0x00000A0284	32	rwNormal read/write	0x00000000	DMA BD20 1
DMA_BD20_2	0x00000A0288	32	rwNormal read/write	0x00000000	DMA BD20 2
DMA_BD20_3	0x00000A028C	32	rwNormal read/write	0x00000000	DMA BD20 3
DMA_BD20_4	0x00000A0290	32	rwNormal read/write	0x00000000	DMA BD20 4
DMA_BD20_5	0x00000A0294	32	rwNormal read/write	0x00000000	DMA BD20 5
DMA_BD20_6	0x00000A0298	32	rwNormal read/write	0x00000000	DMA BD20 6
DMA_BD20_7	0x00000A029C	32	rwNormal read/write	0x00000000	DMA BD20 7
DMA_BD21_0	0x00000A02A0	32	rwNormal read/write	0x00000000	DMA BD21 0
DMA_BD21_1	0x00000A02A4	32	rwNormal read/write	0x00000000	DMA BD21 1
DMA_BD21_2	0x00000A02A8	32	rwNormal read/write	0x00000000	DMA BD21 2
DMA_BD21_3	0x00000A02AC	32	rwNormal read/write	0x00000000	DMA BD21 3
DMA_BD21_4	0x00000A02B0	32	rwNormal read/write	0x00000000	DMA BD21 4
DMA_BD21_5	0x00000A02B4	32	rwNormal read/write	0x00000000	DMA BD21 5
DMA_BD21_6	0x00000A02B8	32	rwNormal read/write	0x00000000	DMA BD21 6
DMA_BD21_7	0x00000A02BC	32	rwNormal read/write	0x00000000	DMA BD21 7
DMA_BD22_0	0x00000A02C0	32	rwNormal read/write	0x00000000	DMA BD22 0
DMA_BD22_1	0x00000A02C4	32	rwNormal read/write	0x00000000	DMA BD22 1
DMA_BD22_2	0x00000A02C8	32	rwNormal read/write	0x00000000	DMA BD22 2
DMA_BD22_3	0x00000A02CC	32	rwNormal read/write	0x00000000	DMA BD22 3
DMA_BD22_4	0x00000A02D0	32	rwNormal read/write	0x00000000	DMA BD22 4
DMA_BD22_5	0x00000A02D4	32	rwNormal read/write	0x00000000	DMA BD22 5
DMA_BD22_6	0x00000A02D8	32	rwNormal read/write	0x00000000	DMA BD22 6
DMA_BD22_7	0x00000A02DC	32	rwNormal read/write	0x00000000	DMA BD22 7
DMA_BD23_0	0x00000A02E0	32	rwNormal read/write	0x00000000	DMA BD23 0
DMA_BD23_1	0x00000A02E4	32	rwNormal read/write	0x00000000	DMA BD23 1
DMA_BD23_2	0x00000A02E8	32	rwNormal read/write	0x00000000	DMA BD23 2
DMA_BD23_3	0x00000A02EC	32	rwNormal read/write	0x00000000	DMA BD23 3
DMA_BD23_4	0x00000A02F0	32	rwNormal read/write	0x00000000	DMA BD23 4
DMA_BD23_5	0x00000A02F4	32	rwNormal read/write	0x00000000	DMA BD23 5
DMA_BD23_6	0x00000A02F8	32	rwNormal read/write	0x00000000	DMA BD23 6
DMA_BD23_7	0x00000A02FC	32	rwNormal read/write	0x00000000	DMA BD23 7
DMA_BD24_0	0x00000A0300	32	rwNormal read/write	0x00000000	DMA BD24 0
DMA_BD24_1	0x00000A0304	32	rwNormal read/write	0x00000000	DMA BD24 1
DMA_BD24_2	0x00000A0308	32	rwNormal read/write	0x00000000	DMA BD24 2
DMA_BD24_3	0x00000A030C	32	rwNormal read/write	0x00000000	DMA BD24 3
DMA_BD24_4	0x00000A0310	32	rwNormal read/write	0x00000000	DMA BD24 4
DMA_BD24_5	0x00000A0314	32	rwNormal read/write	0x00000000	DMA BD24 5
DMA_BD24_6	0x00000A0318	32	rwNormal read/write	0x00000000	DMA BD24 6
DMA_BD24_7	0x00000A031C	32	rwNormal read/write	0x00000000	DMA BD24 7
DMA_BD25_0	0x00000A0320	32	rwNormal read/write	0x00000000	DMA BD25 0
DMA_BD25_1	0x00000A0324	32	rwNormal read/write	0x00000000	DMA BD25 1
DMA_BD25_2	0x00000A0328	32	rwNormal read/write	0x00000000	DMA BD25 2
DMA_BD25_3	0x00000A032C	32	rwNormal read/write	0x00000000	DMA BD25 3
DMA_BD25_4	0x00000A0330	32	rwNormal read/write	0x00000000	DMA BD25 4
DMA_BD25_5	0x00000A0334	32	rwNormal read/write	0x00000000	DMA BD25 5
DMA_BD25_6	0x00000A0338	32	rwNormal read/write	0x00000000	DMA BD25 6
DMA_BD25_7	0x00000A033C	32	rwNormal read/write	0x00000000	DMA BD25 7
DMA_BD26_0	0x00000A0340	32	rwNormal read/write	0x00000000	DMA BD26 0
DMA_BD26_1	0x00000A0344	32	rwNormal read/write	0x00000000	DMA BD26 1
DMA_BD26_2	0x00000A0348	32	rwNormal read/write	0x00000000	DMA BD26 2
DMA_BD26_3	0x00000A034C	32	rwNormal read/write	0x00000000	DMA BD26 3
DMA_BD26_4	0x00000A0350	32	rwNormal read/write	0x00000000	DMA BD26 4
DMA_BD26_5	0x00000A0354	32	rwNormal read/write	0x00000000	DMA BD26 5
DMA_BD26_6	0x00000A0358	32	rwNormal read/write	0x00000000	DMA BD26 6
DMA_BD26_7	0x00000A035C	32	rwNormal read/write	0x00000000	DMA BD26 7
DMA_BD27_0	0x00000A0360	32	rwNormal read/write	0x00000000	DMA BD27 0
DMA_BD27_1	0x00000A0364	32	rwNormal read/write	0x00000000	DMA BD27 1
DMA_BD27_2	0x00000A0368	32	rwNormal read/write	0x00000000	DMA BD27 2
DMA_BD27_3	0x00000A036C	32	rwNormal read/write	0x00000000	DMA BD27 3
DMA_BD27_4	0x00000A0370	32	rwNormal read/write	0x00000000	DMA BD27 4
DMA_BD27_5	0x00000A0374	32	rwNormal read/write	0x00000000	DMA BD27 5
DMA_BD27_6	0x00000A0378	32	rwNormal read/write	0x00000000	DMA BD27 6
DMA_BD27_7	0x00000A037C	32	rwNormal read/write	0x00000000	DMA BD27 7
DMA_BD28_0	0x00000A0380	32	rwNormal read/write	0x00000000	DMA BD28 0
DMA_BD28_1	0x00000A0384	32	rwNormal read/write	0x00000000	DMA BD28 1
DMA_BD28_2	0x00000A0388	32	rwNormal read/write	0x00000000	DMA BD28 2
DMA_BD28_3	0x00000A038C	32	rwNormal read/write	0x00000000	DMA BD28 3
DMA_BD28_4	0x00000A0390	32	rwNormal read/write	0x00000000	DMA BD28 4
DMA_BD28_5	0x00000A0394	32	rwNormal read/write	0x00000000	DMA BD28 5
DMA_BD28_6	0x00000A0398	32	rwNormal read/write	0x00000000	DMA BD28 6
DMA_BD28_7	0x00000A039C	32	rwNormal read/write	0x00000000	DMA BD28 7
DMA_BD29_0	0x00000A03A0	32	rwNormal read/write	0x00000000	DMA BD29 0
DMA_BD29_1	0x00000A03A4	32	rwNormal read/write	0x00000000	DMA BD29 1
DMA_BD29_2	0x00000A03A8	32	rwNormal read/write	0x00000000	DMA BD29 2
DMA_BD29_3	0x00000A03AC	32	rwNormal read/write	0x00000000	DMA BD29 3
DMA_BD29_4	0x00000A03B0	32	rwNormal read/write	0x00000000	DMA BD29 4
DMA_BD29_5	0x00000A03B4	32	rwNormal read/write	0x00000000	DMA BD29 5
DMA_BD29_6	0x00000A03B8	32	rwNormal read/write	0x00000000	DMA BD29 6
DMA_BD29_7	0x00000A03BC	32	rwNormal read/write	0x00000000	DMA BD29 7
DMA_BD30_0	0x00000A03C0	32	rwNormal read/write	0x00000000	DMA BD30 0
DMA_BD30_1	0x00000A03C4	32	rwNormal read/write	0x00000000	DMA BD30 1
DMA_BD30_2	0x00000A03C8	32	rwNormal read/write	0x00000000	DMA BD30 2
DMA_BD30_3	0x00000A03CC	32	rwNormal read/write	0x00000000	DMA BD30 3
DMA_BD30_4	0x00000A03D0	32	rwNormal read/write	0x00000000	DMA BD30 4
DMA_BD30_5	0x00000A03D4	32	rwNormal read/write	0x00000000	DMA BD30 5
DMA_BD30_6	0x00000A03D8	32	rwNormal read/write	0x00000000	DMA BD30 6
DMA_BD30_7	0x00000A03DC	32	rwNormal read/write	0x00000000	DMA BD30 7
DMA_BD31_0	0x00000A03E0	32	rwNormal read/write	0x00000000	DMA BD31 0
DMA_BD31_1	0x00000A03E4	32	rwNormal read/write	0x00000000	DMA BD31 1
DMA_BD31_2	0x00000A03E8	32	rwNormal read/write	0x00000000	DMA BD31 2
DMA_BD31_3	0x00000A03EC	32	rwNormal read/write	0x00000000	DMA BD31 3
DMA_BD31_4	0x00000A03F0	32	rwNormal read/write	0x00000000	DMA BD31 4
DMA_BD31_5	0x00000A03F4	32	rwNormal read/write	0x00000000	DMA BD31 5
DMA_BD31_6	0x00000A03F8	32	rwNormal read/write	0x00000000	DMA BD31 6
DMA_BD31_7	0x00000A03FC	32	rwNormal read/write	0x00000000	DMA BD31 7
DMA_BD32_0	0x00000A0400	32	rwNormal read/write	0x00000000	DMA BD32 0
DMA_BD32_1	0x00000A0404	32	rwNormal read/write	0x00000000	DMA BD32 1
DMA_BD32_2	0x00000A0408	32	rwNormal read/write	0x00000000	DMA BD32 2
DMA_BD32_3	0x00000A040C	32	rwNormal read/write	0x00000000	DMA BD32 3
DMA_BD32_4	0x00000A0410	32	rwNormal read/write	0x00000000	DMA BD32 4
DMA_BD32_5	0x00000A0414	32	rwNormal read/write	0x00000000	DMA BD32 5
DMA_BD32_6	0x00000A0418	32	rwNormal read/write	0x00000000	DMA BD32 6
DMA_BD32_7	0x00000A041C	32	rwNormal read/write	0x00000000	DMA BD32 7
DMA_BD33_0	0x00000A0420	32	rwNormal read/write	0x00000000	DMA BD33 0
DMA_BD33_1	0x00000A0424	32	rwNormal read/write	0x00000000	DMA BD33 1
DMA_BD33_2	0x00000A0428	32	rwNormal read/write	0x00000000	DMA BD33 2
DMA_BD33_3	0x00000A042C	32	rwNormal read/write	0x00000000	DMA BD33 3
DMA_BD33_4	0x00000A0430	32	rwNormal read/write	0x00000000	DMA BD33 4
DMA_BD33_5	0x00000A0434	32	rwNormal read/write	0x00000000	DMA BD33 5
DMA_BD33_6	0x00000A0438	32	rwNormal read/write	0x00000000	DMA BD33 6
DMA_BD33_7	0x00000A043C	32	rwNormal read/write	0x00000000	DMA BD33 7
DMA_BD34_0	0x00000A0440	32	rwNormal read/write	0x00000000	DMA BD34 0
DMA_BD34_1	0x00000A0444	32	rwNormal read/write	0x00000000	DMA BD34 1
DMA_BD34_2	0x00000A0448	32	rwNormal read/write	0x00000000	DMA BD34 2
DMA_BD34_3	0x00000A044C	32	rwNormal read/write	0x00000000	DMA BD34 3
DMA_BD34_4	0x00000A0450	32	rwNormal read/write	0x00000000	DMA BD34 4
DMA_BD34_5	0x00000A0454	32	rwNormal read/write	0x00000000	DMA BD34 5
DMA_BD34_6	0x00000A0458	32	rwNormal read/write	0x00000000	DMA BD34 6
DMA_BD34_7	0x00000A045C	32	rwNormal read/write	0x00000000	DMA BD34 7
DMA_BD35_0	0x00000A0460	32	rwNormal read/write	0x00000000	DMA BD35 0
DMA_BD35_1	0x00000A0464	32	rwNormal read/write	0x00000000	DMA BD35 1
DMA_BD35_2	0x00000A0468	32	rwNormal read/write	0x00000000	DMA BD35 2
DMA_BD35_3	0x00000A046C	32	rwNormal read/write	0x00000000	DMA BD35 3
DMA_BD35_4	0x00000A0470	32	rwNormal read/write	0x00000000	DMA BD35 4
DMA_BD35_5	0x00000A0474	32	rwNormal read/write	0x00000000	DMA BD35 5
DMA_BD35_6	0x00000A0478	32	rwNormal read/write	0x00000000	DMA BD35 6
DMA_BD35_7	0x00000A047C	32	rwNormal read/write	0x00000000	DMA BD35 7
DMA_BD36_0	0x00000A0480	32	rwNormal read/write	0x00000000	DMA BD36 0
DMA_BD36_1	0x00000A0484	32	rwNormal read/write	0x00000000	DMA BD36 1
DMA_BD36_2	0x00000A0488	32	rwNormal read/write	0x00000000	DMA BD36 2
DMA_BD36_3	0x00000A048C	32	rwNormal read/write	0x00000000	DMA BD36 3
DMA_BD36_4	0x00000A0490	32	rwNormal read/write	0x00000000	DMA BD36 4
DMA_BD36_5	0x00000A0494	32	rwNormal read/write	0x00000000	DMA BD36 5
DMA_BD36_6	0x00000A0498	32	rwNormal read/write	0x00000000	DMA BD36 6
DMA_BD36_7	0x00000A049C	32	rwNormal read/write	0x00000000	DMA BD36 7
DMA_BD37_0	0x00000A04A0	32	rwNormal read/write	0x00000000	DMA BD37 0
DMA_BD37_1	0x00000A04A4	32	rwNormal read/write	0x00000000	DMA BD37 1
DMA_BD37_2	0x00000A04A8	32	rwNormal read/write	0x00000000	DMA BD37 2
DMA_BD37_3	0x00000A04AC	32	rwNormal read/write	0x00000000	DMA BD37 3
DMA_BD37_4	0x00000A04B0	32	rwNormal read/write	0x00000000	DMA BD37 4
DMA_BD37_5	0x00000A04B4	32	rwNormal read/write	0x00000000	DMA BD37 5
DMA_BD37_6	0x00000A04B8	32	rwNormal read/write	0x00000000	DMA BD37 6
DMA_BD37_7	0x00000A04BC	32	rwNormal read/write	0x00000000	DMA BD37 7
DMA_BD38_0	0x00000A04C0	32	rwNormal read/write	0x00000000	DMA BD38 0
DMA_BD38_1	0x00000A04C4	32	rwNormal read/write	0x00000000	DMA BD38 1
DMA_BD38_2	0x00000A04C8	32	rwNormal read/write	0x00000000	DMA BD38 2
DMA_BD38_3	0x00000A04CC	32	rwNormal read/write	0x00000000	DMA BD38 3
DMA_BD38_4	0x00000A04D0	32	rwNormal read/write	0x00000000	DMA BD38 4
DMA_BD38_5	0x00000A04D4	32	rwNormal read/write	0x00000000	DMA BD38 5
DMA_BD38_6	0x00000A04D8	32	rwNormal read/write	0x00000000	DMA BD38 6
DMA_BD38_7	0x00000A04DC	32	rwNormal read/write	0x00000000	DMA BD38 7
DMA_BD39_0	0x00000A04E0	32	rwNormal read/write	0x00000000	DMA BD39 0
DMA_BD39_1	0x00000A04E4	32	rwNormal read/write	0x00000000	DMA BD39 1
DMA_BD39_2	0x00000A04E8	32	rwNormal read/write	0x00000000	DMA BD39 2
DMA_BD39_3	0x00000A04EC	32	rwNormal read/write	0x00000000	DMA BD39 3
DMA_BD39_4	0x00000A04F0	32	rwNormal read/write	0x00000000	DMA BD39 4
DMA_BD39_5	0x00000A04F4	32	rwNormal read/write	0x00000000	DMA BD39 5
DMA_BD39_6	0x00000A04F8	32	rwNormal read/write	0x00000000	DMA BD39 6
DMA_BD39_7	0x00000A04FC	32	rwNormal read/write	0x00000000	DMA BD39 7
DMA_BD40_0	0x00000A0500	32	rwNormal read/write	0x00000000	DMA BD40 0
DMA_BD40_1	0x00000A0504	32	rwNormal read/write	0x00000000	DMA BD40 1
DMA_BD40_2	0x00000A0508	32	rwNormal read/write	0x00000000	DMA BD40 2
DMA_BD40_3	0x00000A050C	32	rwNormal read/write	0x00000000	DMA BD40 3
DMA_BD40_4	0x00000A0510	32	rwNormal read/write	0x00000000	DMA BD40 4
DMA_BD40_5	0x00000A0514	32	rwNormal read/write	0x00000000	DMA BD40 5
DMA_BD40_6	0x00000A0518	32	rwNormal read/write	0x00000000	DMA BD40 6
DMA_BD40_7	0x00000A051C	32	rwNormal read/write	0x00000000	DMA BD40 7
DMA_BD41_0	0x00000A0520	32	rwNormal read/write	0x00000000	DMA BD41 0
DMA_BD41_1	0x00000A0524	32	rwNormal read/write	0x00000000	DMA BD41 1
DMA_BD41_2	0x00000A0528	32	rwNormal read/write	0x00000000	DMA BD41 2
DMA_BD41_3	0x00000A052C	32	rwNormal read/write	0x00000000	DMA BD41 3
DMA_BD41_4	0x00000A0530	32	rwNormal read/write	0x00000000	DMA BD41 4
DMA_BD41_5	0x00000A0534	32	rwNormal read/write	0x00000000	DMA BD41 5
DMA_BD41_6	0x00000A0538	32	rwNormal read/write	0x00000000	DMA BD41 6
DMA_BD41_7	0x00000A053C	32	rwNormal read/write	0x00000000	DMA BD41 7
DMA_BD42_0	0x00000A0540	32	rwNormal read/write	0x00000000	DMA BD42 0
DMA_BD42_1	0x00000A0544	32	rwNormal read/write	0x00000000	DMA BD42 1
DMA_BD42_2	0x00000A0548	32	rwNormal read/write	0x00000000	DMA BD42 2
DMA_BD42_3	0x00000A054C	32	rwNormal read/write	0x00000000	DMA BD42 3
DMA_BD42_4	0x00000A0550	32	rwNormal read/write	0x00000000	DMA BD42 4
DMA_BD42_5	0x00000A0554	32	rwNormal read/write	0x00000000	DMA BD42 5
DMA_BD42_6	0x00000A0558	32	rwNormal read/write	0x00000000	DMA BD42 6
DMA_BD42_7	0x00000A055C	32	rwNormal read/write	0x00000000	DMA BD42 7
DMA_BD43_0	0x00000A0560	32	rwNormal read/write	0x00000000	DMA BD43 0
DMA_BD43_1	0x00000A0564	32	rwNormal read/write	0x00000000	DMA BD43 1
DMA_BD43_2	0x00000A0568	32	rwNormal read/write	0x00000000	DMA BD43 2
DMA_BD43_3	0x00000A056C	32	rwNormal read/write	0x00000000	DMA BD43 3
DMA_BD43_4	0x00000A0570	32	rwNormal read/write	0x00000000	DMA BD43 4
DMA_BD43_5	0x00000A0574	32	rwNormal read/write	0x00000000	DMA BD43 5
DMA_BD43_6	0x00000A0578	32	rwNormal read/write	0x00000000	DMA BD43 6
DMA_BD43_7	0x00000A057C	32	rwNormal read/write	0x00000000	DMA BD43 7
DMA_BD44_0	0x00000A0580	32	rwNormal read/write	0x00000000	DMA BD44 0
DMA_BD44_1	0x00000A0584	32	rwNormal read/write	0x00000000	DMA BD44 1
DMA_BD44_2	0x00000A0588	32	rwNormal read/write	0x00000000	DMA BD44 2
DMA_BD44_3	0x00000A058C	32	rwNormal read/write	0x00000000	DMA BD44 3
DMA_BD44_4	0x00000A0590	32	rwNormal read/write	0x00000000	DMA BD44 4
DMA_BD44_5	0x00000A0594	32	rwNormal read/write	0x00000000	DMA BD44 5
DMA_BD44_6	0x00000A0598	32	rwNormal read/write	0x00000000	DMA BD44 6
DMA_BD44_7	0x00000A059C	32	rwNormal read/write	0x00000000	DMA BD44 7
DMA_BD45_0	0x00000A05A0	32	rwNormal read/write	0x00000000	DMA BD45 0
DMA_BD45_1	0x00000A05A4	32	rwNormal read/write	0x00000000	DMA BD45 1
DMA_BD45_2	0x00000A05A8	32	rwNormal read/write	0x00000000	DMA BD45 2
DMA_BD45_3	0x00000A05AC	32	rwNormal read/write	0x00000000	DMA BD45 3
DMA_BD45_4	0x00000A05B0	32	rwNormal read/write	0x00000000	DMA BD45 4
DMA_BD45_5	0x00000A05B4	32	rwNormal read/write	0x00000000	DMA BD45 5
DMA_BD45_6	0x00000A05B8	32	rwNormal read/write	0x00000000	DMA BD45 6
DMA_BD45_7	0x00000A05BC	32	rwNormal read/write	0x00000000	DMA BD45 7
DMA_BD46_0	0x00000A05C0	32	rwNormal read/write	0x00000000	DMA BD46 0
DMA_BD46_1	0x00000A05C4	32	rwNormal read/write	0x00000000	DMA BD46 1
DMA_BD46_2	0x00000A05C8	32	rwNormal read/write	0x00000000	DMA BD46 2
DMA_BD46_3	0x00000A05CC	32	rwNormal read/write	0x00000000	DMA BD46 3
DMA_BD46_4	0x00000A05D0	32	rwNormal read/write	0x00000000	DMA BD46 4
DMA_BD46_5	0x00000A05D4	32	rwNormal read/write	0x00000000	DMA BD46 5
DMA_BD46_6	0x00000A05D8	32	rwNormal read/write	0x00000000	DMA BD46 6
DMA_BD46_7	0x00000A05DC	32	rwNormal read/write	0x00000000	DMA BD46 7
DMA_BD47_0	0x00000A05E0	32	rwNormal read/write	0x00000000	DMA BD47 0
DMA_BD47_1	0x00000A05E4	32	rwNormal read/write	0x00000000	DMA BD47 1
DMA_BD47_2	0x00000A05E8	32	rwNormal read/write	0x00000000	DMA BD47 2
DMA_BD47_3	0x00000A05EC	32	rwNormal read/write	0x00000000	DMA BD47 3
DMA_BD47_4	0x00000A05F0	32	rwNormal read/write	0x00000000	DMA BD47 4
DMA_BD47_5	0x00000A05F4	32	rwNormal read/write	0x00000000	DMA BD47 5
DMA_BD47_6	0x00000A05F8	32	rwNormal read/write	0x00000000	DMA BD47 6
DMA_BD47_7	0x00000A05FC	32	rwNormal read/write	0x00000000	DMA BD47 7
DMA_S2MM_0_Ctrl	0x00000A0600	32	rwNormal read/write	0x00000000	DMA Control Register S2MM Ch0
DMA_S2MM_0_Start_Queue	0x00000A0604	32	woWrite-only	0x00000000	DMA Control Register S2MM Ch0 start BD
DMA_S2MM_1_Ctrl	0x00000A0608	32	rwNormal read/write	0x00000000	DMA Control Register S2MM Ch1
DMA_S2MM_1_Start_Queue	0x00000A060C	32	woWrite-only	0x00000000	DMA Control Register S2MM Ch1 start BD
DMA_S2MM_2_Ctrl	0x00000A0610	32	rwNormal read/write	0x00000000	DMA Control Register S2MM Ch2
DMA_S2MM_2_Start_Queue	0x00000A0614	32	woWrite-only	0x00000000	DMA Control Register S2MM Ch2 start BD
DMA_S2MM_3_Ctrl	0x00000A0618	32	rwNormal read/write	0x00000000	DMA Control Register S2MM Ch3
DMA_S2MM_3_Start_Queue	0x00000A061C	32	woWrite-only	0x00000000	DMA Control Register S2MM Ch3 start BD
DMA_S2MM_4_Ctrl	0x00000A0620	32	rwNormal read/write	0x00000000	DMA Control Register S2MM Ch4
DMA_S2MM_4_Start_Queue	0x00000A0624	32	woWrite-only	0x00000000	DMA Control Register S2MM Ch4 start BD
DMA_S2MM_5_Ctrl	0x00000A0628	32	rwNormal read/write	0x00000000	DMA Control Register S2MM Ch5
DMA_S2MM_5_Start_Queue	0x00000A062C	32	woWrite-only	0x00000000	DMA Control Register S2MM Ch5 start BD
DMA_MM2S_0_Ctrl	0x00000A0630	32	rwNormal read/write	0x00000000	DMA Control Register MM2S Ch0
DMA_MM2S_0_Start_Queue	0x00000A0634	32	woWrite-only	0x00000000	DMA Control Register MM2S Ch0 start BD
DMA_MM2S_1_Ctrl	0x00000A0638	32	rwNormal read/write	0x00000000	DMA Control Register MM2S Ch1
DMA_MM2S_1_Start_Queue	0x00000A063C	32	woWrite-only	0x00000000	DMA Control Register MM2S Ch1 start BD
DMA_MM2S_2_Ctrl	0x00000A0640	32	rwNormal read/write	0x00000000	DMA Control Register MM2S Ch2
DMA_MM2S_2_Start_Queue	0x00000A0644	32	woWrite-only	0x00000000	DMA Control Register MM2S Ch2 start BD
DMA_MM2S_3_Ctrl	0x00000A0648	32	rwNormal read/write	0x00000000	DMA Control Register MM2S Ch3
DMA_MM2S_3_Start_Queue	0x00000A064C	32	woWrite-only	0x00000000	DMA Control Register MM2S Ch3 start BD
DMA_MM2S_4_Ctrl	0x00000A0650	32	rwNormal read/write	0x00000000	DMA Control Register MM2S Ch4
DMA_MM2S_4_Start_Queue	0x00000A0654	32	woWrite-only	0x00000000	DMA Control Register MM2S Ch4 start BD
DMA_MM2S_5_Ctrl	0x00000A0658	32	rwNormal read/write	0x00000000	DMA Control Register MM2S Ch5
DMA_MM2S_5_Start_Queue	0x00000A065C	32	woWrite-only	0x00000000	DMA Control Register MM2S Ch5 start BD
DMA_S2MM_Status_0	0x00000A0660	32	mixedMixed types. See bit-field details.	0x00000000	DMA S2MM Status Register Ch0
DMA_S2MM_Status_1	0x00000A0664	32	mixedMixed types. See bit-field details.	0x00000000	DMA S2MM Status Register Ch1
DMA_S2MM_Status_2	0x00000A0668	32	mixedMixed types. See bit-field details.	0x00000000	DMA S2MM Status Register Ch2
DMA_S2MM_Status_3	0x00000A066C	32	mixedMixed types. See bit-field details.	0x00000000	DMA S2MM Status Register Ch3
DMA_S2MM_Status_4	0x00000A0670	32	mixedMixed types. See bit-field details.	0x00000000	DMA S2MM Status Register Ch4
DMA_S2MM_Status_5	0x00000A0674	32	mixedMixed types. See bit-field details.	0x00000000	DMA S2MM Status Register Ch5
DMA_MM2S_Status_0	0x00000A0680	32	mixedMixed types. See bit-field details.	0x00000000	DMA MM2S Status Register Ch0
DMA_MM2S_Status_1	0x00000A0684	32	mixedMixed types. See bit-field details.	0x00000000	DMA MM2S Status Register Ch1
DMA_MM2S_Status_2	0x00000A0688	32	mixedMixed types. See bit-field details.	0x00000000	DMA MM2S Status Register Ch2
DMA_MM2S_Status_3	0x00000A068C	32	mixedMixed types. See bit-field details.	0x00000000	DMA MM2S Status Register Ch3
DMA_MM2S_Status_4	0x00000A0690	32	mixedMixed types. See bit-field details.	0x00000000	DMA MM2S Status Register Ch4
DMA_MM2S_Status_5	0x00000A0694	32	mixedMixed types. See bit-field details.	0x00000000	DMA MM2S Status Register Ch5
DMA_Event_Channel_Selection	0x00000A06A0	32	rwNormal read/write	0x00000000	Selection of which DMA channels will generate events
DMA_S2MM_Current_Write_Count_0	0x00000A06B0	32	roRead-only	0x00000000	DMA S2MM Current Write Count Ch0
DMA_S2MM_Current_Write_Count_1	0x00000A06B4	32	roRead-only	0x00000000	DMA S2MM Current Write Count Ch1
DMA_S2MM_Current_Write_Count_2	0x00000A06B8	32	roRead-only	0x00000000	DMA S2MM Current Write Count Ch2
DMA_S2MM_Current_Write_Count_3	0x00000A06BC	32	roRead-only	0x00000000	DMA S2MM Current Write Count Ch3
DMA_S2MM_Current_Write_Count_4	0x00000A06C0	32	roRead-only	0x00000000	DMA S2MM Current Write Count Ch4
DMA_S2MM_Current_Write_Count_5	0x00000A06C4	32	roRead-only	0x00000000	DMA S2MM Current Write Count Ch5
DMA_S2MM_FoT_Count_FIFO_Pop_0	0x00000A06C8	32	roRead-only	0x00000000	DMA S2MM FoT Count FIFO Pop Ch0
DMA_S2MM_FoT_Count_FIFO_Pop_1	0x00000A06CC	32	roRead-only	0x00000000	DMA S2MM FoT Count FIFO Pop Ch1
DMA_S2MM_FoT_Count_FIFO_Pop_2	0x00000A06D0	32	roRead-only	0x00000000	DMA S2MM FoT Count FIFO Pop Ch2
DMA_S2MM_FoT_Count_FIFO_Pop_3	0x00000A06D4	32	roRead-only	0x00000000	DMA S2MM FoT Count FIFO Pop Ch3
DMA_S2MM_FoT_Count_FIFO_Pop_4	0x00000A06D8	32	roRead-only	0x00000000	DMA S2MM FoT Count FIFO Pop Ch4
DMA_S2MM_FoT_Count_FIFO_Pop_5	0x00000A06DC	32	roRead-only	0x00000000	DMA S2MM FoT Count FIFO Pop Ch5
Stream_Switch_Master_Config_DMA0	0x00000B0000	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration DMA 0
Stream_Switch_Master_Config_DMA1	0x00000B0004	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration DMA 1
Stream_Switch_Master_Config_DMA2	0x00000B0008	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration DMA 2
Stream_Switch_Master_Config_DMA3	0x00000B000C	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration DMA 3
Stream_Switch_Master_Config_DMA4	0x00000B0010	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration DMA 4
Stream_Switch_Master_Config_DMA5	0x00000B0014	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration DMA 5
Stream_Switch_Master_Config_Tile_Ctrl	0x00000B0018	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration AI Engine Tile Ctrl
Stream_Switch_Master_Config_South0	0x00000B001C	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration South 0
Stream_Switch_Master_Config_South1	0x00000B0020	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration South 1
Stream_Switch_Master_Config_South2	0x00000B0024	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration South 2
Stream_Switch_Master_Config_South3	0x00000B0028	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration South 3
Stream_Switch_Master_Config_North0	0x00000B002C	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration North 0
Stream_Switch_Master_Config_North1	0x00000B0030	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration North 1
Stream_Switch_Master_Config_North2	0x00000B0034	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration North 2
Stream_Switch_Master_Config_North3	0x00000B0038	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration North 3
Stream_Switch_Master_Config_North4	0x00000B003C	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration North 4
Stream_Switch_Master_Config_North5	0x00000B0040	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration North 5
Stream_Switch_Slave_Config_DMA_0	0x00000B0100	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 0
Stream_Switch_Slave_Config_DMA_1	0x00000B0104	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 1
Stream_Switch_Slave_Config_DMA_2	0x00000B0108	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 2
Stream_Switch_Slave_Config_DMA_3	0x00000B010C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 3
Stream_Switch_Slave_Config_DMA_4	0x00000B0110	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 4
Stream_Switch_Slave_Config_DMA_5	0x00000B0114	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 5
Stream_Switch_Slave_Config_Tile_Ctrl	0x00000B0118	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Tile Ctrl
Stream_Switch_Slave_Config_South_0	0x00000B011C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 0
Stream_Switch_Slave_Config_South_1	0x00000B0120	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 1
Stream_Switch_Slave_Config_South_2	0x00000B0124	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 2
Stream_Switch_Slave_Config_South_3	0x00000B0128	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 3
Stream_Switch_Slave_Config_South_4	0x00000B012C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 4
Stream_Switch_Slave_Config_South_5	0x00000B0130	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 5
Stream_Switch_Slave_Config_North_0	0x00000B0134	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 0
Stream_Switch_Slave_Config_North_1	0x00000B0138	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 1
Stream_Switch_Slave_Config_North_2	0x00000B013C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 2
Stream_Switch_Slave_Config_North_3	0x00000B0140	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 3
Stream_Switch_Slave_Config_Trace	0x00000B0144	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Trace
Stream_Switch_Slave_DMA_0_Slot0	0x00000B0200	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 0
Stream_Switch_Slave_DMA_0_Slot1	0x00000B0204	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 0
Stream_Switch_Slave_DMA_0_Slot2	0x00000B0208	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 0
Stream_Switch_Slave_DMA_0_Slot3	0x00000B020C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 0
Stream_Switch_Slave_DMA_1_Slot0	0x00000B0210	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 1
Stream_Switch_Slave_DMA_1_Slot1	0x00000B0214	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 1
Stream_Switch_Slave_DMA_1_Slot2	0x00000B0218	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 1
Stream_Switch_Slave_DMA_1_Slot3	0x00000B021C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 1
Stream_Switch_Slave_DMA_2_Slot0	0x00000B0220	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 2
Stream_Switch_Slave_DMA_2_Slot1	0x00000B0224	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 2
Stream_Switch_Slave_DMA_2_Slot2	0x00000B0228	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 2
Stream_Switch_Slave_DMA_2_Slot3	0x00000B022C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 2
Stream_Switch_Slave_DMA_3_Slot0	0x00000B0230	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 3
Stream_Switch_Slave_DMA_3_Slot1	0x00000B0234	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 3
Stream_Switch_Slave_DMA_3_Slot2	0x00000B0238	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 3
Stream_Switch_Slave_DMA_3_Slot3	0x00000B023C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 3
Stream_Switch_Slave_DMA_4_Slot0	0x00000B0240	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 4
Stream_Switch_Slave_DMA_4_Slot1	0x00000B0244	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 4
Stream_Switch_Slave_DMA_4_Slot2	0x00000B0248	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 4
Stream_Switch_Slave_DMA_4_Slot3	0x00000B024C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 4
Stream_Switch_Slave_DMA_5_Slot0	0x00000B0250	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 5
Stream_Switch_Slave_DMA_5_Slot1	0x00000B0254	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 5
Stream_Switch_Slave_DMA_5_Slot2	0x00000B0258	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 5
Stream_Switch_Slave_DMA_5_Slot3	0x00000B025C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 5
Stream_Switch_Slave_Tile_Ctrl_Slot0	0x00000B0260	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Tile Ctrl
Stream_Switch_Slave_Tile_Ctrl_Slot1	0x00000B0264	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Tile Ctrl
Stream_Switch_Slave_Tile_Ctrl_Slot2	0x00000B0268	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Tile Ctrl
Stream_Switch_Slave_Tile_Ctrl_Slot3	0x00000B026C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Tile Ctrl
Stream_Switch_Slave_South_0_Slot0	0x00000B0270	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 0
Stream_Switch_Slave_South_0_Slot1	0x00000B0274	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 0
Stream_Switch_Slave_South_0_Slot2	0x00000B0278	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 0
Stream_Switch_Slave_South_0_Slot3	0x00000B027C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 0
Stream_Switch_Slave_South_1_Slot0	0x00000B0280	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 1
Stream_Switch_Slave_South_1_Slot1	0x00000B0284	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 1
Stream_Switch_Slave_South_1_Slot2	0x00000B0288	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 1
Stream_Switch_Slave_South_1_Slot3	0x00000B028C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 1
Stream_Switch_Slave_South_2_Slot0	0x00000B0290	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 2
Stream_Switch_Slave_South_2_Slot1	0x00000B0294	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 2
Stream_Switch_Slave_South_2_Slot2	0x00000B0298	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 2
Stream_Switch_Slave_South_2_Slot3	0x00000B029C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 2
Stream_Switch_Slave_South_3_Slot0	0x00000B02A0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 3
Stream_Switch_Slave_South_3_Slot1	0x00000B02A4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 3
Stream_Switch_Slave_South_3_Slot2	0x00000B02A8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 3
Stream_Switch_Slave_South_3_Slot3	0x00000B02AC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 3
Stream_Switch_Slave_South_4_Slot0	0x00000B02B0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 4
Stream_Switch_Slave_South_4_Slot1	0x00000B02B4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 4
Stream_Switch_Slave_South_4_Slot2	0x00000B02B8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 4
Stream_Switch_Slave_South_4_Slot3	0x00000B02BC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 4
Stream_Switch_Slave_South_5_Slot0	0x00000B02C0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 5
Stream_Switch_Slave_South_5_Slot1	0x00000B02C4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 5
Stream_Switch_Slave_South_5_Slot2	0x00000B02C8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 5
Stream_Switch_Slave_South_5_Slot3	0x00000B02CC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 5
Stream_Switch_Slave_North_0_Slot0	0x00000B02D0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 0
Stream_Switch_Slave_North_0_Slot1	0x00000B02D4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 0
Stream_Switch_Slave_North_0_Slot2	0x00000B02D8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 0
Stream_Switch_Slave_North_0_Slot3	0x00000B02DC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 0
Stream_Switch_Slave_North_1_Slot0	0x00000B02E0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 1
Stream_Switch_Slave_North_1_Slot1	0x00000B02E4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 1
Stream_Switch_Slave_North_1_Slot2	0x00000B02E8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 1
Stream_Switch_Slave_North_1_Slot3	0x00000B02EC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 1
Stream_Switch_Slave_North_2_Slot0	0x00000B02F0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 2
Stream_Switch_Slave_North_2_Slot1	0x00000B02F4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 2
Stream_Switch_Slave_North_2_Slot2	0x00000B02F8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 2
Stream_Switch_Slave_North_2_Slot3	0x00000B02FC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 2
Stream_Switch_Slave_North_3_Slot0	0x00000B0300	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 3
Stream_Switch_Slave_North_3_Slot1	0x00000B0304	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 3
Stream_Switch_Slave_North_3_Slot2	0x00000B0308	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 3
Stream_Switch_Slave_North_3_Slot3	0x00000B030C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 3
Stream_Switch_Slave_Trace_Slot0	0x00000B0310	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine Trace
Stream_Switch_Slave_Trace_Slot1	0x00000B0314	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine Trace
Stream_Switch_Slave_Trace_Slot2	0x00000B0318	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine Trace
Stream_Switch_Slave_Trace_Slot3	0x00000B031C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine Trace
Stream_Switch_Deterministic_Merge_arb0_slave0_1	0x00000B0800	32	rwNormal read/write	0x00000000	Stream Switch Deterministic Merge Arbiter:0 Slave:0,1
Stream_Switch_Deterministic_Merge_arb0_slave2_3	0x00000B0804	32	rwNormal read/write	0x00000000	Stream Switch Deterministic Merge Arbiter:0 Slave:2,3
Stream_Switch_Deterministic_Merge_arb0_ctrl	0x00000B0808	32	rwNormal read/write	0x00000000	Stream Switch Deterministic Merge Arbiter:0 Control
Stream_Switch_Deterministic_Merge_arb1_slave0_1	0x00000B0810	32	rwNormal read/write	0x00000000	Stream Switch Deterministic Merge Arbiter:1 Slave:0,1
Stream_Switch_Deterministic_Merge_arb1_slave2_3	0x00000B0814	32	rwNormal read/write	0x00000000	Stream Switch Deterministic Merge Arbiter:1 Slave:2,3
Stream_Switch_Deterministic_Merge_arb1_ctrl	0x00000B0818	32	rwNormal read/write	0x00000000	Stream Switch Deterministic Merge Arbiter:1 Control
Stream_Switch_Event_Port_Selection_0	0x00000B0F00	32	rwNormal read/write	0x00000000	Select Stream Switch Ports for event generation
Stream_Switch_Event_Port_Selection_1	0x00000B0F04	32	rwNormal read/write	0x00000000	Select Stream Switch Ports for event generation
Stream_Switch_Parity_Status	0x00000B0F10	32	wtcReadable, write a 1 to clear	0x00000000	Status bits for Parity errors on stream switch ports
Stream_Switch_Parity_Injection	0x00000B0F20	32	rwNormal read/write	0x00000000	Injection of Parity errors on stream switch ports
Tile_Control_Packet_Handler_Status	0x00000B0F30	32	wtcReadable, write a 1 to clear	0x00000000	Status of control packet handling
Stream_Switch_Adaptive_Clock_Gate_Status	0x00000B0F34	32	roRead-only	0x00000000	Status of Stream Switch Adaptive Clock Gate
Stream_Switch_Adaptive_Clock_Gate_Abort_Period	0x00000B0F38	32	rwNormal read/write	0x00000007	Status of Stream Switch Adaptive Clock Gate Abort Period
Lock0_value	0x00000C0000	32	rwNormal read/write	0x00000000	Value of lock 0
Lock1_value	0x00000C0010	32	rwNormal read/write	0x00000000	Value of lock 1
Lock2_value	0x00000C0020	32	rwNormal read/write	0x00000000	Value of lock 2
Lock3_value	0x00000C0030	32	rwNormal read/write	0x00000000	Value of lock 3
Lock4_value	0x00000C0040	32	rwNormal read/write	0x00000000	Value of lock 4
Lock5_value	0x00000C0050	32	rwNormal read/write	0x00000000	Value of lock 5
Lock6_value	0x00000C0060	32	rwNormal read/write	0x00000000	Value of lock 6
Lock7_value	0x00000C0070	32	rwNormal read/write	0x00000000	Value of lock 7
Lock8_value	0x00000C0080	32	rwNormal read/write	0x00000000	Value of lock 8
Lock9_value	0x00000C0090	32	rwNormal read/write	0x00000000	Value of lock 9
Lock10_value	0x00000C00A0	32	rwNormal read/write	0x00000000	Value of lock 10
Lock11_value	0x00000C00B0	32	rwNormal read/write	0x00000000	Value of lock 11
Lock12_value	0x00000C00C0	32	rwNormal read/write	0x00000000	Value of lock 12
Lock13_value	0x00000C00D0	32	rwNormal read/write	0x00000000	Value of lock 13
Lock14_value	0x00000C00E0	32	rwNormal read/write	0x00000000	Value of lock 14
Lock15_value	0x00000C00F0	32	rwNormal read/write	0x00000000	Value of lock 15
Lock16_value	0x00000C0100	32	rwNormal read/write	0x00000000	Value of lock 16
Lock17_value	0x00000C0110	32	rwNormal read/write	0x00000000	Value of lock 17
Lock18_value	0x00000C0120	32	rwNormal read/write	0x00000000	Value of lock 18
Lock19_value	0x00000C0130	32	rwNormal read/write	0x00000000	Value of lock 19
Lock20_value	0x00000C0140	32	rwNormal read/write	0x00000000	Value of lock 20
Lock21_value	0x00000C0150	32	rwNormal read/write	0x00000000	Value of lock 21
Lock22_value	0x00000C0160	32	rwNormal read/write	0x00000000	Value of lock 22
Lock23_value	0x00000C0170	32	rwNormal read/write	0x00000000	Value of lock 23
Lock24_value	0x00000C0180	32	rwNormal read/write	0x00000000	Value of lock 24
Lock25_value	0x00000C0190	32	rwNormal read/write	0x00000000	Value of lock 25
Lock26_value	0x00000C01A0	32	rwNormal read/write	0x00000000	Value of lock 26
Lock27_value	0x00000C01B0	32	rwNormal read/write	0x00000000	Value of lock 27
Lock28_value	0x00000C01C0	32	rwNormal read/write	0x00000000	Value of lock 28
Lock29_value	0x00000C01D0	32	rwNormal read/write	0x00000000	Value of lock 29
Lock30_value	0x00000C01E0	32	rwNormal read/write	0x00000000	Value of lock 30
Lock31_value	0x00000C01F0	32	rwNormal read/write	0x00000000	Value of lock 31
Lock32_value	0x00000C0200	32	rwNormal read/write	0x00000000	Value of lock 32
Lock33_value	0x00000C0210	32	rwNormal read/write	0x00000000	Value of lock 33
Lock34_value	0x00000C0220	32	rwNormal read/write	0x00000000	Value of lock 34
Lock35_value	0x00000C0230	32	rwNormal read/write	0x00000000	Value of lock 35
Lock36_value	0x00000C0240	32	rwNormal read/write	0x00000000	Value of lock 36
Lock37_value	0x00000C0250	32	rwNormal read/write	0x00000000	Value of lock 37
Lock38_value	0x00000C0260	32	rwNormal read/write	0x00000000	Value of lock 38
Lock39_value	0x00000C0270	32	rwNormal read/write	0x00000000	Value of lock 39
Lock40_value	0x00000C0280	32	rwNormal read/write	0x00000000	Value of lock 40
Lock41_value	0x00000C0290	32	rwNormal read/write	0x00000000	Value of lock 41
Lock42_value	0x00000C02A0	32	rwNormal read/write	0x00000000	Value of lock 42
Lock43_value	0x00000C02B0	32	rwNormal read/write	0x00000000	Value of lock 43
Lock44_value	0x00000C02C0	32	rwNormal read/write	0x00000000	Value of lock 44
Lock45_value	0x00000C02D0	32	rwNormal read/write	0x00000000	Value of lock 45
Lock46_value	0x00000C02E0	32	rwNormal read/write	0x00000000	Value of lock 46
Lock47_value	0x00000C02F0	32	rwNormal read/write	0x00000000	Value of lock 47
Lock48_value	0x00000C0300	32	rwNormal read/write	0x00000000	Value of lock 48
Lock49_value	0x00000C0310	32	rwNormal read/write	0x00000000	Value of lock 49
Lock50_value	0x00000C0320	32	rwNormal read/write	0x00000000	Value of lock 50
Lock51_value	0x00000C0330	32	rwNormal read/write	0x00000000	Value of lock 51
Lock52_value	0x00000C0340	32	rwNormal read/write	0x00000000	Value of lock 52
Lock53_value	0x00000C0350	32	rwNormal read/write	0x00000000	Value of lock 53
Lock54_value	0x00000C0360	32	rwNormal read/write	0x00000000	Value of lock 54
Lock55_value	0x00000C0370	32	rwNormal read/write	0x00000000	Value of lock 55
Lock56_value	0x00000C0380	32	rwNormal read/write	0x00000000	Value of lock 56
Lock57_value	0x00000C0390	32	rwNormal read/write	0x00000000	Value of lock 57
Lock58_value	0x00000C03A0	32	rwNormal read/write	0x00000000	Value of lock 58
Lock59_value	0x00000C03B0	32	rwNormal read/write	0x00000000	Value of lock 59
Lock60_value	0x00000C03C0	32	rwNormal read/write	0x00000000	Value of lock 60
Lock61_value	0x00000C03D0	32	rwNormal read/write	0x00000000	Value of lock 61
Lock62_value	0x00000C03E0	32	rwNormal read/write	0x00000000	Value of lock 62
Lock63_value	0x00000C03F0	32	rwNormal read/write	0x00000000	Value of lock 63
Locks_Event_Selection_0	0x00000C0400	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 0
Locks_Event_Selection_1	0x00000C0404	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 1
Locks_Event_Selection_2	0x00000C0408	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 2
Locks_Event_Selection_3	0x00000C040C	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 3
Locks_Event_Selection_4	0x00000C0410	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 4
Locks_Event_Selection_5	0x00000C0414	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 5
Locks_Event_Selection_6	0x00000C0418	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 6
Locks_Event_Selection_7	0x00000C041C	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 7
Locks_Overflow_0	0x00000C0420	32	wtcReadable, write a 1 to clear	0x00000000	Status bits for lock overflow, write to clear
Locks_Overflow_1	0x00000C0424	32	wtcReadable, write a 1 to clear	0x00000000	Status bits for lock overflow, write to clear
Locks_Underflow_0	0x00000C0428	32	wtcReadable, write a 1 to clear	0x00000000	Status bits for lock underflow, write to clear
Locks_Underflow_1	0x00000C042C	32	wtcReadable, write a 1 to clear	0x00000000	Status bits for lock underflow, write to clear
Lock_Request	0x00000D0000	32	roRead-only	0x00000000	Lock Request. 64kB address space: 0xD0000 - 0xDFFFC, Lock_Id [15:10], Acq/nRel (Acq=1, Rel=0) (9), Change_Value [8:2]
Module_Clock_Control	0x00000FFF00	32	rwNormal read/write	0x00000033	Control clock gating of modules (privileged)