DMA_BD1_4 (MEMORY_TILE_MODULE) Register Description

Register NameDMA_BD1_4
Offset Address0x00000A0030
Absolute Address

The notation for the AI Engine register addresses is aie_[pl]/[core]/[memory]/[noc]_module_column_row.

Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDMA BD1 4

DMA_BD1_4 (MEMORY_TILE_MODULE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Enable_Compression31rwNormal read/write0Enable Compression (MM2S), decompression (S2MM). Only effective if channel has (de)compression enabled
D2_Zero_Before30:27rwNormal read/write0Add this many zero wraps of dim1 before dim2 (MM2S only)
D2_Wrap26:17rwNormal read/write0Wrap after this many dim2 steps and increment dim3 by a step. 0=do not wrap
D2_Stepsize16:0rwNormal read/write0Offset each step for dimension 2 (number of 32-bit words) (actual -1); Range [1:128k]