| Register Name | Stream_Switch_Master_Config_DMA0 |
|---|---|
| Offset Address | 0x000003F004 |
| Absolute Address |
The notation for the AI Engine register addresses is aie_[pl]/[core]/[memory]/[noc]_module_column_row. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Stream Switch Master Configuration DMA 0 |
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Master_Enable | 31 | rwNormal read/write | 0x0 | 1=enable the master port |
| Packet_Enable | 30 | rwNormal read/write | 0x0 | 0=circuit; 1=packet switching mode for master port |
| Drop_Header | 7 | rwNormal read/write | 0x0 | 1=drop header on packet if in packet switching mode, ignored in circuit switching mode |
| Configuration | 6:0 | rwNormal read/write | 0x0 | circuit: [4:0]=slave port; packet: [2:0]=arbitor, [6:3]=msel_enable |