| Register Name | DMA_MM2S_1_Ctrl |
|---|---|
| Offset Address | 0x000001DE18 |
| Absolute Address |
The notation for the AI Engine register addresses is aie_[pl]/[core]/[memory]/[noc]_module_column_row. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | DMA Control Register MM2S Ch1 |
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Controller_ID | 15:8 | rwNormal read/write | 0x0 | Task-complete-token controller ID field |
| Compression_Enable | 4 | rwNormal read/write | 0x0 | Enable compression. 0=no compression; 1=compression may be enabled by BD |
| Reset | 1 | rwNormal read/write | 0x0 | Reset MM2S0 |
| Reserved | 0 | rwNormal read/write | 0x0 | Reserved (previously Enable) |