Overview - Traditional Designs

Training Modules

Create Custom PL IP Blocks and RTL Modules

Block Design Creation

Create Vitis™ Platform for Embedded Software

Adopt Best RTL Practices

Adopt Clocking Practice

Leverage Existing IP

Create Custom IP Using HLS

Design Examples

Perform Functional Verification

Evaluate the Vivado Synthesis, Place, and Route OOC

Synthesis and Implementation

Simulation

Implementation

Embedded Software Development

UG1273 - Design Flows
UG1273 - System Migration
UG1387 - Design Planning
UG1387 - Using Modular NoC in RTL Designs
UG1387 - Design Planning for Key IP Blocks
UG1388 - Versal Adaptive SoC System Integration and Validation Methodology Guide

Designing FPGAs Using the Vivado Design Suite 1
Designing FPGAs Using the Vivado Design Suite 2
Designing FPGAs Using the Vivado Design Suite 3
Designing FPGAs Using the Vivado Design Suite 4
Modular NoC Tutorials
Designing with the Versal Adaptive SoC: Architecture
Designing with the Versal Adaptive SoC: Design Methodology
Designing with the Versal Adaptive SoC: NoC
Designing with the Versal Adaptive SoC: Memory Interfaces
Designing with Versal AI Engine: Quick Start
Designing with the Versal Adaptive SoC: Serial Transceivers
Designing with the Versal Adaptive SoC: Hardware Debug
Designing with the Versal Adaptive SoCs: Quick Start
Migrating to the Vitis Unified IDE
High-Level Synthesis with the Vitis HLS Tool
Designing with the IP Integrator Tool
UG1387 - Using Modular NoC in RTL Designs

UG1387 - Design Creation with Block Designs
UG994 - Working with Block Designs
UG995 - Vivado Design Suite Tutorial: Designing IP Subsystems Using IP Integrator Tutorial
PG352 - Control Interfaces and Processing System LogiCORE IP Product Guide
PG450 - Processing System Wizard LogiCORE IP Product Guide
PG313 - Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide
PG406 - Programmable Network on Chip (NoC2) LogiCORE IP Product Guide
PG456 - Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide
UG994 - Referencing a Module
NoC and DDRMC Design
PG331 - Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide
UG908 - Vivado Design Suite User Guide: Programming and Debugging
UG892 - Source Management and Revision Control Recommendations
UG896 - Using Revision and Source Control

PG352 - Control Interfaces and Processing System LogiCORE IP Product Guide
PG450 - Processing System Wizard LogiCORE IP Product Guide
UG1701 - Creating and Using Vitis Platforms

UG1387 - Design Creation with RTL
UG901 - Vivado Design Suite User Guide: Synthesis

UG1387 - Clocking Guidelines

UG896 - IP Basics
UG939 - Vivado Design Suite Tutorial: Designing with IP
UG1118 - Vivado Design Suite User Guide: Creating and Packaging Custom IP
UG1119 - Vivado Design Suite Tutorial: Creating and Packaging Custom IP

UG1399 - Benefits of High-Level Synthesis
UG1399 - Target Flow Overview
UG1399 - Design Principles
UG1399 - Optimizing Techniques and Troubleshooting Tips
Code Examples
UG1399 - Running C/RTL Co-Simulation
Vitis Libraries

Versal Example Designs

UG900 - Running Functional Simulation
UG937 - Logic Simulation Tutorial

UG1387 - Design Implementation

UG1388 - Simulation Flows

UG1387 - Design Implementation

Embedded Software Development

Overview - Platform-based Designs

Training Modules

Create Hardware Platform in Vivado

Create Vivado Project with Extensible Vitis Platform Enabled

Create Vitis Platforms

Introduction to Vitis Platforms

Vitis Flows for AI Engine Designs and PL/RTL Kernels

Create Vitis Platforms

Create PL Kernels Using RTL

Understand the Kernel Requirements

Package RTL Code as PL Kernels

Create PL Kernels Using HLS

Introduction to Vitis HLS

Coding and Optimization

Verify the PL Kernel

Vitis HLS Libraries

Next Steps

AI Engine Development

Simulation and Implementation

Embedded Software Development

UG1273 - Design Flows
UG1273 - System Migration
UG1387 - Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide
UG1388 - Versal Adaptive SoC System Integration and Validation Methodology Guide
UG1700 - Data Center Acceleration Using Vitis User Guide

Designing with the Versal Adaptive SoC: Architecture
Designing with the Versal Adaptive SoC: Design Methodology
Designing with the Versal Adaptive SoC: NoC
High-Level Synthesis with the Vitis HLS Tool
Designing with Versal AI Engine: Architecture and Design Flow - 1
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
Designing with Versal AI Engine: Kernel Programming and Optimization - 3
Designing with the Versal Adaptive SoC: Memory Interfaces
Designing with Versal AI Engine: Quick Start
Designing with the Versal Adaptive SoC: Serial Transceivers
Designing with the Versal Adaptive SoC: Hardware Debug
Designing with the Versal Adaptive SoCs: Quick Start
Accelerating Applications with the Vitis Unified Software Environment
Migrating to the Vitis Unified IDE

XD101 - Create a Vitis Platform for Custom Versal Boards
PG352 - Control Interfaces and Processing System LogiCORE IP
PG450 - Processing System Wizard LogiCORE IP Product Guide
UG1701 - Embedded Design Development Using Vitis User Guide

UG1701 - Creating and Using Vitis Platforms

UG1701 - Vitis Integrated Flow
UG1701 - Vitis Export to Vivado Flow
UG1701 - Vitis Subsystem Flow

XD101 - Vitis Tutorials: Vitis Platform Creation
UG1400 - Creating a Platform Component from XSA
UG1305 - Versal Adaptive SoC Embedded Design Tutorial
UG1701 - Simulation and Verification in Vitis

UG1700 - Requirements of an RTL Kernel

UG1700 - RTL Kernel Development Flow
XD099 - RTL Systems Integration Example
XD099 - Bottom-up RTL Kernel Flow with Vitis for Acceleration

Vitis HLS Tools Overview
UG1399 - Design Principles
UG1399 - Target Flow Overview

UG1399 - Design Principles
UG1399 - Optimizating Techniques and Troubleshooting Tips
Code Examples

UG1399 - Running C/RTL Co-Simulation

UG1399 - Vitis HLS Libraries Reference
Vitis Libraries

AI Engine Development

System Integration and Validation

Embedded Software Development

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