MEMORY_MODULE Module

MEMORY_MODULE Module Description

Module Type	MEMORY_MODULE Module
Base Addresses	The register base addresses for compute modules can be found by using the following formula: Register Base Address = 0x200_0000_0000 + (<colnum> * 32 + <rownum + m + 1>) * 0x10_0000 Note 1: The first row of compute tiles is rownum 0. Note 2: m is the number of memory tile rows, which is 1 or 2 depending on the device. For the calculated addresses for each device, see Answer Record 000036946.
Description	Memory Module Control and Status Registers

Module Type

Base Addresses

The register base addresses for compute modules can be found by using the following formula:
   Register Base Address = 0x200_0000_0000 + (<colnum> * 32 + <rownum + m + 1>) * 0x10_0000
   Note 1: The first row of compute tiles is rownum 0.
   Note 2: m is the number of memory tile rows, which is 1 or 2 depending on the device.

For the calculated addresses for each device, see Answer Record 000036946.

Description

Memory Module Control and Status Registers

MEMORY_MODULE Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
DataMemory	0x0000000000	128	rwNormal read/write	0x00000000	DataMemory of 8 banks, 128-bit wide, 64kB
Performance_Control0	0x0000011000	32	rwNormal read/write	0x00000000	Performance Counters Start and Stop Event
Performance_Control1	0x0000011008	32	rwNormal read/write	0x00000000	Performance Counters Reset Event
Performance_Counter0	0x0000011020	32	rwNormal read/write	0x00000000	Performance Counter0
Performance_Counter1	0x0000011024	32	rwNormal read/write	0x00000000	Performance Counter1
Performance_Counter0_Event_Value	0x0000011080	32	rwNormal read/write	0x00000000	Performance Counter0 Event Value.
Performance_Counter1_Event_Value	0x0000011084	32	rwNormal read/write	0x00000000	Performance Counter1 Event Value.
Timer_Control	0x0000014000	32	mixedMixed types. See bit-field details.	0x00000000	Control of Internal Timer
Event_Generate	0x0000014008	32	woWrite-only	0x00000000	Generate an internal event
Event_Broadcast0	0x0000014010	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast0
Event_Broadcast1	0x0000014014	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast1
Event_Broadcast2	0x0000014018	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast2
Event_Broadcast3	0x000001401C	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast3
Event_Broadcast4	0x0000014020	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast4
Event_Broadcast5	0x0000014024	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast5
Event_Broadcast6	0x0000014028	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast6
Event_Broadcast7	0x000001402C	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast7
Event_Broadcast8	0x0000014030	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast8
Event_Broadcast9	0x0000014034	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast9
Event_Broadcast10	0x0000014038	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast10
Event_Broadcast11	0x000001403C	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast11
Event_Broadcast12	0x0000014040	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast12
Event_Broadcast13	0x0000014044	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast13
Event_Broadcast14	0x0000014048	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast14
Event_Broadcast15	0x000001404C	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast15
Event_Broadcast_Block_South_Set	0x0000014050	32	woWrite-only	0x00000000	Set block of broadcast signals to South
Event_Broadcast_Block_South_Clr	0x0000014054	32	woWrite-only	0x00000000	Clear block of broadcast signals to South
Event_Broadcast_Block_South_Value	0x0000014058	32	roRead-only	0x00000000	Current value of block for broadcast signals to South
Event_Broadcast_Block_West_Set	0x0000014060	32	woWrite-only	0x00000000	Set block of broadcast signals to West
Event_Broadcast_Block_West_Clr	0x0000014064	32	woWrite-only	0x00000000	Clear block of broadcast signals to West
Event_Broadcast_Block_West_Value	0x0000014068	32	roRead-only	0x00000000	Current value of block for broadcast signals to West
Event_Broadcast_Block_North_Set	0x0000014070	32	woWrite-only	0x00000000	Set block of broadcast signals to North
Event_Broadcast_Block_North_Clr	0x0000014074	32	woWrite-only	0x00000000	Clear block of broadcast signals to North
Event_Broadcast_Block_North_Value	0x0000014078	32	roRead-only	0x00000000	Current value of block for broadcast signals to North
Event_Broadcast_Block_East_Set	0x0000014080	32	woWrite-only	0x00000000	Set block of broadcast signals to East
Event_Broadcast_Block_East_Clr	0x0000014084	32	woWrite-only	0x00000000	Clear block of broadcast signals to East
Event_Broadcast_Block_East_Value	0x0000014088	32	roRead-only	0x00000000	Current value of block for broadcast signals to East
Trace_Control0	0x00000140D0	32	rwNormal read/write	0x00000000	Control of Trace
Trace_Control1	0x00000140D4	32	rwNormal read/write	0x00000000	Control of Trace: packet configuration
Trace_Status	0x00000140D8	32	roRead-only	0x00000000	Status of trace engine
Trace_Event0	0x00000140E0	32	rwNormal read/write	0x00000000	Control of which Internal Event to Trace
Trace_Event1	0x00000140E4	32	rwNormal read/write	0x00000000	Control of which Internal Event to Trace
Timer_Trig_Event_Low_Value	0x00000140F0	32	rwNormal read/write	0xFFFFFFFF	Internal Timer Event Value.
Timer_Trig_Event_High_Value	0x00000140F4	32	rwNormal read/write	0xFFFFFFFF	Internal Timer Event Value.
Timer_Low	0x00000140F8	32	roRead-only	0x00000000	Internal Timer Low part Value.
Timer_High	0x00000140FC	32	roRead-only	0x00000000	Internal Timer High part Value.
WatchPoint0	0x0000014100	32	rwNormal read/write	0x00000000	Define Watchpoint0
WatchPoint1	0x0000014104	32	rwNormal read/write	0x00000000	Define Watchpoint1
Event_Status0	0x0000014200	32	wtcReadable, write a 1 to clear	0x00000002	Internal event status register0
Event_Status1	0x0000014204	32	wtcReadable, write a 1 to clear	0x00000000	Internal event status register1
Event_Status2	0x0000014208	32	wtcReadable, write a 1 to clear	0x00000000	Internal event status register2
Event_Status3	0x000001420C	32	wtcReadable, write a 1 to clear	0x00000000	Internal event status register3
Combo_event_inputs	0x0000014400	32	rwNormal read/write	0x00000000	Combo events input events
Combo_event_control	0x0000014404	32	rwNormal read/write	0x00000000	Combo events input events
Edge_Detection_event_control	0x0000014408	32	rwNormal read/write	0x00000000	Configuration for edge detection events
Event_Group_0_Enable	0x0000014500	32	rwNormal read/write	0x000003FF	Event enable for Group 0
Event_Group_Watchpoint_Enable	0x0000014504	32	rwNormal read/write	0x00000003	Event enable for Watchpoint Group
Event_Group_DMA_Enable	0x0000014508	32	rwNormal read/write	0x00FFFFFF	Event enable for DMA Group
Event_Group_Lock_Enable	0x000001450C	32	rwNormal read/write	0xFFFFFFFF	Event enable for Lock Group
Event_Group_Memory_Conflict_Enable	0x0000014510	32	rwNormal read/write	0x000000FF	Event enable for Memory Conflict Group
Event_Group_Error_Enable	0x0000014514	32	rwNormal read/write	0x0000FFFF	Event enable for Error Group
Event_Group_Broadcast_Enable	0x0000014518	32	rwNormal read/write	0x0000FFFF	Event enable for Broadcast Group
Event_Group_User_Event_Enable	0x000001451C	32	rwNormal read/write	0x0000000F	Event enable for User Group
Memory_Control	0x0000016010	32	rwNormal read/write	0x00000000	Control for memory (privileged)
DMA_BD0_0	0x000001D000	32	rwNormal read/write	0x00000000	DMA BD0 0
DMA_BD0_1	0x000001D004	32	rwNormal read/write	0x00000000	DMA BD0 1
DMA_BD0_2	0x000001D008	32	rwNormal read/write	0x00000000	DMA BD0 2
DMA_BD0_3	0x000001D00C	32	rwNormal read/write	0x00000000	DMA BD0 3
DMA_BD0_4	0x000001D010	32	rwNormal read/write	0x00000000	DMA BD0 4
DMA_BD0_5	0x000001D014	32	rwNormal read/write	0x00000000	DMA BD0 5
DMA_BD1_0	0x000001D020	32	rwNormal read/write	0x00000000	DMA BD1 0
DMA_BD1_1	0x000001D024	32	rwNormal read/write	0x00000000	DMA BD1 1
DMA_BD1_2	0x000001D028	32	rwNormal read/write	0x00000000	DMA BD1 2
DMA_BD1_3	0x000001D02C	32	rwNormal read/write	0x00000000	DMA BD1 3
DMA_BD1_4	0x000001D030	32	rwNormal read/write	0x00000000	DMA BD1 4
DMA_BD1_5	0x000001D034	32	rwNormal read/write	0x00000000	DMA BD1 5
DMA_BD2_0	0x000001D040	32	rwNormal read/write	0x00000000	DMA BD2 0
DMA_BD2_1	0x000001D044	32	rwNormal read/write	0x00000000	DMA BD2 1
DMA_BD2_2	0x000001D048	32	rwNormal read/write	0x00000000	DMA BD2 2
DMA_BD2_3	0x000001D04C	32	rwNormal read/write	0x00000000	DMA BD2 3
DMA_BD2_4	0x000001D050	32	rwNormal read/write	0x00000000	DMA BD2 4
DMA_BD2_5	0x000001D054	32	rwNormal read/write	0x00000000	DMA BD2 5
DMA_BD3_0	0x000001D060	32	rwNormal read/write	0x00000000	DMA BD3 0
DMA_BD3_1	0x000001D064	32	rwNormal read/write	0x00000000	DMA BD3 1
DMA_BD3_2	0x000001D068	32	rwNormal read/write	0x00000000	DMA BD3 2
DMA_BD3_3	0x000001D06C	32	rwNormal read/write	0x00000000	DMA BD3 3
DMA_BD3_4	0x000001D070	32	rwNormal read/write	0x00000000	DMA BD3 4
DMA_BD3_5	0x000001D074	32	rwNormal read/write	0x00000000	DMA BD3 5
DMA_BD4_0	0x000001D080	32	rwNormal read/write	0x00000000	DMA BD4 0
DMA_BD4_1	0x000001D084	32	rwNormal read/write	0x00000000	DMA BD4 1
DMA_BD4_2	0x000001D088	32	rwNormal read/write	0x00000000	DMA BD4 2
DMA_BD4_3	0x000001D08C	32	rwNormal read/write	0x00000000	DMA BD4 3
DMA_BD4_4	0x000001D090	32	rwNormal read/write	0x00000000	DMA BD4 4
DMA_BD4_5	0x000001D094	32	rwNormal read/write	0x00000000	DMA BD4 5
DMA_BD5_0	0x000001D0A0	32	rwNormal read/write	0x00000000	DMA BD5 0
DMA_BD5_1	0x000001D0A4	32	rwNormal read/write	0x00000000	DMA BD5 1
DMA_BD5_2	0x000001D0A8	32	rwNormal read/write	0x00000000	DMA BD5 2
DMA_BD5_3	0x000001D0AC	32	rwNormal read/write	0x00000000	DMA BD5 3
DMA_BD5_4	0x000001D0B0	32	rwNormal read/write	0x00000000	DMA BD5 4
DMA_BD5_5	0x000001D0B4	32	rwNormal read/write	0x00000000	DMA BD5 5
DMA_BD6_0	0x000001D0C0	32	rwNormal read/write	0x00000000	DMA BD6 0
DMA_BD6_1	0x000001D0C4	32	rwNormal read/write	0x00000000	DMA BD6 1
DMA_BD6_2	0x000001D0C8	32	rwNormal read/write	0x00000000	DMA BD6 2
DMA_BD6_3	0x000001D0CC	32	rwNormal read/write	0x00000000	DMA BD6 3
DMA_BD6_4	0x000001D0D0	32	rwNormal read/write	0x00000000	DMA BD6 4
DMA_BD6_5	0x000001D0D4	32	rwNormal read/write	0x00000000	DMA BD6 5
DMA_BD7_0	0x000001D0E0	32	rwNormal read/write	0x00000000	DMA BD7 0
DMA_BD7_1	0x000001D0E4	32	rwNormal read/write	0x00000000	DMA BD7 1
DMA_BD7_2	0x000001D0E8	32	rwNormal read/write	0x00000000	DMA BD7 2
DMA_BD7_3	0x000001D0EC	32	rwNormal read/write	0x00000000	DMA BD7 3
DMA_BD7_4	0x000001D0F0	32	rwNormal read/write	0x00000000	DMA BD7 4
DMA_BD7_5	0x000001D0F4	32	rwNormal read/write	0x00000000	DMA BD7 5
DMA_BD8_0	0x000001D100	32	rwNormal read/write	0x00000000	DMA BD8 0
DMA_BD8_1	0x000001D104	32	rwNormal read/write	0x00000000	DMA BD8 1
DMA_BD8_2	0x000001D108	32	rwNormal read/write	0x00000000	DMA BD8 2
DMA_BD8_3	0x000001D10C	32	rwNormal read/write	0x00000000	DMA BD8 3
DMA_BD8_4	0x000001D110	32	rwNormal read/write	0x00000000	DMA BD8 4
DMA_BD8_5	0x000001D114	32	rwNormal read/write	0x00000000	DMA BD8 5
DMA_BD9_0	0x000001D120	32	rwNormal read/write	0x00000000	DMA BD9 0
DMA_BD9_1	0x000001D124	32	rwNormal read/write	0x00000000	DMA BD9 1
DMA_BD9_2	0x000001D128	32	rwNormal read/write	0x00000000	DMA BD9 2
DMA_BD9_3	0x000001D12C	32	rwNormal read/write	0x00000000	DMA BD9 3
DMA_BD9_4	0x000001D130	32	rwNormal read/write	0x00000000	DMA BD9 4
DMA_BD9_5	0x000001D134	32	rwNormal read/write	0x00000000	DMA BD9 5
DMA_BD10_0	0x000001D140	32	rwNormal read/write	0x00000000	DMA BD10 0
DMA_BD10_1	0x000001D144	32	rwNormal read/write	0x00000000	DMA BD10 1
DMA_BD10_2	0x000001D148	32	rwNormal read/write	0x00000000	DMA BD10 2
DMA_BD10_3	0x000001D14C	32	rwNormal read/write	0x00000000	DMA BD10 3
DMA_BD10_4	0x000001D150	32	rwNormal read/write	0x00000000	DMA BD10 4
DMA_BD10_5	0x000001D154	32	rwNormal read/write	0x00000000	DMA BD10 5
DMA_BD11_0	0x000001D160	32	rwNormal read/write	0x00000000	DMA BD11 0
DMA_BD11_1	0x000001D164	32	rwNormal read/write	0x00000000	DMA BD11 1
DMA_BD11_2	0x000001D168	32	rwNormal read/write	0x00000000	DMA BD11 2
DMA_BD11_3	0x000001D16C	32	rwNormal read/write	0x00000000	DMA BD11 3
DMA_BD11_4	0x000001D170	32	rwNormal read/write	0x00000000	DMA BD11 4
DMA_BD11_5	0x000001D174	32	rwNormal read/write	0x00000000	DMA BD11 5
DMA_BD12_0	0x000001D180	32	rwNormal read/write	0x00000000	DMA BD12 0
DMA_BD12_1	0x000001D184	32	rwNormal read/write	0x00000000	DMA BD12 1
DMA_BD12_2	0x000001D188	32	rwNormal read/write	0x00000000	DMA BD12 2
DMA_BD12_3	0x000001D18C	32	rwNormal read/write	0x00000000	DMA BD12 3
DMA_BD12_4	0x000001D190	32	rwNormal read/write	0x00000000	DMA BD12 4
DMA_BD12_5	0x000001D194	32	rwNormal read/write	0x00000000	DMA BD12 5
DMA_BD13_0	0x000001D1A0	32	rwNormal read/write	0x00000000	DMA BD13 0
DMA_BD13_1	0x000001D1A4	32	rwNormal read/write	0x00000000	DMA BD13 1
DMA_BD13_2	0x000001D1A8	32	rwNormal read/write	0x00000000	DMA BD13 2
DMA_BD13_3	0x000001D1AC	32	rwNormal read/write	0x00000000	DMA BD13 3
DMA_BD13_4	0x000001D1B0	32	rwNormal read/write	0x00000000	DMA BD13 4
DMA_BD13_5	0x000001D1B4	32	rwNormal read/write	0x00000000	DMA BD13 5
DMA_BD14_0	0x000001D1C0	32	rwNormal read/write	0x00000000	DMA BD14 0
DMA_BD14_1	0x000001D1C4	32	rwNormal read/write	0x00000000	DMA BD14 1
DMA_BD14_2	0x000001D1C8	32	rwNormal read/write	0x00000000	DMA BD14 2
DMA_BD14_3	0x000001D1CC	32	rwNormal read/write	0x00000000	DMA BD14 3
DMA_BD14_4	0x000001D1D0	32	rwNormal read/write	0x00000000	DMA BD14 4
DMA_BD14_5	0x000001D1D4	32	rwNormal read/write	0x00000000	DMA BD14 5
DMA_BD15_0	0x000001D1E0	32	rwNormal read/write	0x00000000	DMA BD15 01
DMA_BD15_1	0x000001D1E4	32	rwNormal read/write	0x00000000	DMA BD15 1
DMA_BD15_2	0x000001D1E8	32	rwNormal read/write	0x00000000	DMA BD15 2
DMA_BD15_3	0x000001D1EC	32	rwNormal read/write	0x00000000	DMA BD15 3
DMA_BD15_4	0x000001D1F0	32	rwNormal read/write	0x00000000	DMA BD15 4
DMA_BD15_5	0x000001D1F4	32	rwNormal read/write	0x00000000	DMA BD15 5
DMA_S2MM_0_Ctrl	0x000001DE00	32	rwNormal read/write	0x00000000	DMA Control Register S2MM Ch0
DMA_S2MM_0_Start_Queue	0x000001DE04	32	woWrite-only	0x00000000	DMA Control Register S2MM Ch0
DMA_S2MM_1_Ctrl	0x000001DE08	32	rwNormal read/write	0x00000000	DMA Control Register S2MM Ch1
DMA_S2MM_1_Start_Queue	0x000001DE0C	32	woWrite-only	0x00000000	DMA Control Register S2MM Ch1
DMA_MM2S_0_Ctrl	0x000001DE10	32	rwNormal read/write	0x00000000	DMA Control Register MM2S Ch0
DMA_MM2S_0_Start_Queue	0x000001DE14	32	woWrite-only	0x00000000	DMA Control Register MM2S Ch0
DMA_MM2S_1_Ctrl	0x000001DE18	32	rwNormal read/write	0x00000000	DMA Control Register MM2S Ch1
DMA_MM2S_1_Start_Queue	0x000001DE1C	32	woWrite-only	0x00000000	DMA Control Register MM2S Ch1
DMA_S2MM_Status_0	0x000001DF00	32	mixedMixed types. See bit-field details.	0x00000000	DMA S2MM Status Register Ch0
DMA_S2MM_Status_1	0x000001DF04	32	mixedMixed types. See bit-field details.	0x00000000	DMA S2MM Status Register Ch1
DMA_MM2S_Status_0	0x000001DF10	32	mixedMixed types. See bit-field details.	0x00000000	DMA MM2S Status Register Ch0
DMA_MM2S_Status_1	0x000001DF14	32	mixedMixed types. See bit-field details.	0x00000000	DMA MM2S Status Register Ch1
DMA_S2MM_Current_Write_Count_0	0x000001DF18	32	roRead-only	0x00000000	DMA S2MM Current Write Count Ch0
DMA_S2MM_Current_Write_Count_1	0x000001DF1C	32	roRead-only	0x00000000	DMA S2MM Current Write Count Ch1
DMA_S2MM_FoT_Count_FIFO_Pop_0	0x000001DF20	32	roRead-only	0x00000000	DMA S2MM FoT Count FIFO Pop Ch0
DMA_S2MM_FoT_Count_FIFO_Pop_1	0x000001DF24	32	roRead-only	0x00000000	DMA S2MM FoT Count FIFO Pop Ch1
Lock0_value	0x000001F000	32	rwNormal read/write	0x00000000	Value of lock 0
Lock1_value	0x000001F010	32	rwNormal read/write	0x00000000	Value of lock 1
Lock2_value	0x000001F020	32	rwNormal read/write	0x00000000	Value of lock 2
Lock3_value	0x000001F030	32	rwNormal read/write	0x00000000	Value of lock 3
Lock4_value	0x000001F040	32	rwNormal read/write	0x00000000	Value of lock 4
Lock5_value	0x000001F050	32	rwNormal read/write	0x00000000	Value of lock 5
Lock6_value	0x000001F060	32	rwNormal read/write	0x00000000	Value of lock 6
Lock7_value	0x000001F070	32	rwNormal read/write	0x00000000	Value of lock 7
Lock8_value	0x000001F080	32	rwNormal read/write	0x00000000	Value of lock 8
Lock9_value	0x000001F090	32	rwNormal read/write	0x00000000	Value of lock 9
Lock10_value	0x000001F0A0	32	rwNormal read/write	0x00000000	Value of lock 10
Lock11_value	0x000001F0B0	32	rwNormal read/write	0x00000000	Value of lock 11
Lock12_value	0x000001F0C0	32	rwNormal read/write	0x00000000	Value of lock 12
Lock13_value	0x000001F0D0	32	rwNormal read/write	0x00000000	Value of lock 13
Lock14_value	0x000001F0E0	32	rwNormal read/write	0x00000000	Value of lock 14
Lock15_value	0x000001F0F0	32	rwNormal read/write	0x00000000	Value of lock 15
Locks_Event_Selection_0	0x000001F100	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 0
Locks_Event_Selection_1	0x000001F104	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 1
Locks_Event_Selection_2	0x000001F108	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 2
Locks_Event_Selection_3	0x000001F10C	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 3
Locks_Event_Selection_4	0x000001F110	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 4
Locks_Event_Selection_5	0x000001F114	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 5
Locks_Event_Selection_6	0x000001F118	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 6
Locks_Event_Selection_7	0x000001F11C	32	rwNormal read/write	0x0000003F	Select lock for lock event generation 7
Locks_Overflow	0x000001F120	32	wtcReadable, write a 1 to clear	0x00000000	Status bits for lock overflow, write to clear
Locks_Underflow	0x000001F128	32	wtcReadable, write a 1 to clear	0x00000000	Status bits for lock underflow, write to clear
Lock_Request	0x0000040000	32	roRead-only	0x00000000	Lock Request. 16kB address space: 0x40000 - 0x43FFC, Lock_Id [13:10], Acq/nRel (Acq=1, Rel=0) (9), Change_Value [8:2]