Product Overview	Design Files
Model Composer Product Overview
Design and Simulate an Algorithm Using Vitis Model Composer
Implementing FIR Filters in AMD Versal Adaptive SoC Devices
MathWorks - Designing AI Engines of AMD Versal Adaptive SoC using Simulink and Vitis Model Composer
MathWorks - FPGA Design and Codesign
Tutorial Designs	Design Files
GitHub - Vitis Model Composer Examples and Tutorials
Vitis Tutorials
User Guides	Design Files
UG1483 - Vitis Model Composer User Guide
UG1076 - AI Engine Tools and Flows User Guide
UG1079 - AI Engine Kernel and Graph Programming Guide
UG1393 - Vitis Unified Software Platform Documentation: Application Acceleration Development
UG896 - Vivado Design Suite User Guide: Designing with IP
UG1118 - Vivado Design Suite User Guide: Creating and Packaging Custom IP
Application Notes	Design Files
XAPP1376 - PID Controller Design with Model Composer for Versal Adaptive SoCs	Reference Design Files
XAPP1341 - PID Controller Design with Model Composer Application Note	Reference Design Files

Release Notes
AMD Vitis Model Composer Product Page - What's New
Frequently Asked Questions (FAQ)
AR59432 - When Is a License Checked Out?
Forums and Training
Forums - DSP IP & Tools
Vitis Model Composer: A MATLAB and Simulink-based Product