The AI Engine-ML consists of a matrix of Tiles, Memory Tiles, and Interface Tiles, each containing one or more Modules:
The register base addresses for compute modules can be found by using the following formula:
Register Base Address = 0x200_0000_0000 + (<colnum> * 32 + <rownum + m + 1>) * 0x10_0000
Note 1: The first row of compute tiles is rownum 0.
Note 2: m is the number of memory tile rows, which is 1 or 2 depending on the device.
For the calculated addresses for each device, see Answer Record 000036946.
The register base addresses for memory tile modules can be found by using the following formula:
Register Base Address = 0x200_0000_0000 + (<colnum> * 32 + <rownum + 1>) * 0x10_0000
Note: The first row of memory tiles is rownum 0.
For the calculated addresses for each device, see Answer Record 000036946.
The register base addresses for interface modules can be found by using the following formula:
Register Base Address = 0x200_0000_0000 + (<colnum> * 32) * 0x10_0000
Note: Not all columns have a NOC module.
For the calculated addresses for each device, see Answer Record 000036946.
| Module Type | Description |
|---|---|
| CORE_MODULE | Core Module Control and Status Registers |
| MEMORY_MODULE | Memory Module Control and Status Registers |
| MEMORY_TILE_MODULE | Memory Tile Control and Status Registers |
| NOC_MODULE | NoC Interface Control and Status Registers |
| PL_MODULE | PL Interface Control and Status Registers |