Introduction
Synthesizing the Design
UG901 - Vivado Design Suite User Guide: Synthesis
Key Concepts
Running Design Rule Checks (DRCs) in Vivado
UG901 - Using Block Synthesis
UG1118 - Creating and Packaging Custom IP
UG901 - Using Third-Party Synthesis Tools with Vivado IP
UG901 - Manually Setting a Bottom-Up Flow and Importing Netlists
UG901 - SystemVerilog Constructs
Frequently Asked Questions (FAQ)
UG901 - Why Does a AMD IP Not Get Flattened Completely?
UG901 - What Is the Purpose of the "RuntimeOptimized" Option When Passed to the -directive Switch?
UG901 - What Is the Purpose of the "out_of_context" Option Used as Part of the -mode switch?
UG901 - How Do I Run Bottom-Up Synthesis Using the Vivado Synthesis Tool?
AR51088 - Does VSS Generate Block RAMs for Dual Port RAM When Both Ports Are Specified in the Same Always/Process Block?
AR55194 - What Are Vivado Synthesis Best Practices for System Verilog?
AR55942 - Why Are the Inputs to My EDIF/NGC Files Left Unconnected?

Videos
Advanced Synthesis using Vivado
Using IP with 3rd Party Synthesis Tools
Vivado IP Constraints Overview
Compilation Units in Vivado Synthesis
User Guides
UG949 - Recommended Synthesis and Implementation Methodology
UG835 - Vivado Design Suite Tcl Command Reference Guide
UG912 - Vivado Design Suite Properties Reference Guide
Training
Designing FPGAs Using the Vivado Design Suite

Solution Center and Known Issues
AR55265 - AMD Solution Center for Vivado Synthesis
AR70644 - 2018.x Vivado Synthesis - Known Issues
Design Assistants for Vivado Synthesis
AR51360 - Help with SystemVerilog Support
AR55160 - Help with Synthesis HDL Attribute Support
AR55182 - Help with "synth_design" Tcl Command
AR55185 - Help with Vivado Synthesis's Equivalent RTL/GUI/Tcl Options for XST
AR55260 - XDC Synthesis Attributes and Timing Constraints Support
Forums
AMD User Community Forums - Synthesis
AMD User Community Forums - Vivado Tcl Community