Guided - AI Engine
Guided - AI Engine-ML
Pre-Filtered
Overview
Overview
Training Modules
Develop AI Engine Kernels and Graph
Versal Design Partitioning (incl. AI Engine Array)
Libraries for AI Engine
Develop the AI Engine Kernel and Graph
Verify the Algorithm, Test, and Validate AI Engine Kernels in Vitis
Develop in MATLAB and Simulink Using Vitis Model Composer
Simulate and Debug the AI Engine Graph
Debugging
Performance Analysis and Optimization
Test Hardware and Debug the AI Engine Graph
Create a Verification Subsystem for Hardware Testing
Integrate AIE and Other Domains with the Verification Subsystem
Validate Subsystem Using Hardware Emulation
Test and Debug AIE Graph in Hardware
Overview
Overview
XD100 -
Vitis Tutorials: AI Engine Development
AI Engine web page
AI Engine Series Articles
AI Engine - DSP Design Process
AR75837 -
AI Engine Solution Center
AR75790 -
AIE Compiler - General Guidance and Known Issues
AR75788 -
AIE Simulator - General Guidance and Known Issues
Training Modules
Designing with Versal AI Engine: Quick Start
Designing with Versal AI Engine 1: Architecture and Design Flow
Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
Designing with Versal AI Engine 3: Kernel Programming and Optimization
XD100 -
Designing with the AI Engine DSPLib and Vitis Model Composer
Develop AI Engine Kernels and Graph
Versal Design Partitioning (incl. AI Engine Array)
UG1273 -
System Design Methodology
AM009 -
Versal Adaptive SoC AI Engine Architecture Manual
UG1504 -
System Design Planning Methodology Flow
XD100 -
Versal AI Engine LeNet Tutorial
XD100 -
Super Sampling Rate FIR Filters: Implementation on the AI Engine
XD100 -
Beamforming Tutorial
XD100 -
Versal 2D-FFT Implementation Using Vitis Acceleration Library Tutorial
XD100 -
System Partitioning of a Hough Transform on AI Engine
XD100 -
64K-Pt IFFT @ 2 Gsps Using a 2D Architecture
XD100 -
Versal AI Engine/HLS FIR Filter Tutorial
XD100 -
N-Body Simulator
Libraries for AI Engine
Vitis Libraries GitHub Repository
Vitis Libraries Documentation
DSP Library
Vision Library
XD100 -
AI Engine DSP Library Tutorial
XD100 -
Versal 2D-FFT Implementation Using Vitis Acceleration Library Tutorial
XD100 -
Versal AI Engine/HLS FIR Filter Tutorial
XD100 -
Designing with the AI Engine DSPLib and Vitis Model Composer
XD100 -
Signal Processing on AI Engine Using Vitis DSP Libraries and Vitis Model Composer
Develop the AI Engine Kernel and Graph
UG1076 -
AI Engine Tools and Flows User Guide
UG1079 -
AI Engine Kernel and Graph Programming Guide
UG1529 -
AI Engine API User Guide
UG1078 -
AI Engine Intrinsics User Guide
UG1701 -
Vitis Functional Simulation
UG1701 -
Vitis Subsystem Flow
UG1079 -
Example Designs Using the AI Engine API
XD100 -
AI Engine Run-time Parameter Reconfiguration Tutorial
XD100 -
Floating Point Example Design
XD100 -
Implementing an IIR Filter on the AI Engine
XD100 -
AI Engine Compiler Features
XD100 -
Polyphase Channelizer
XD100 -
Prime Factor FFT
XD100 -
64K IFFT Using 2D Architecture
XD100 -
DDC Chain: Converting from Intrinsics to API
XD100 -
Bilinear Interpolation
XD100 -
Versal Custom Thin Platform Extensible System
XD100 -
Compiling AI Engine Graphs for Independent Partitions
XD100 -
Softmax
XD100 -
MUSIC Algorithm
Verify the Algorithm, Test, and Validate AI Engine Kernels in Vitis
UG1076 -
Simulating an AI Engine Graph Application
AI Engine Test Harness
XD100 -
AI Engine Debug with X86simulator
Develop in MATLAB and Simulink Using Vitis Model Composer
UG1483 -
Vitis Model Composer User Guide
Vitis Model Composer resources on GitHub
XD100 -
Designing with the AI Engine DSPLib and Vitis Model Composer
XD100 -
Signal Processing on AI Engine Using Vitis DSP Libraries and Vitis Model Composer
Simulate and Debug the AI Engine Graph
Debugging
UG1076 -
Compiling an AI Engine Graph Application
UG1076 -
Simulating an AI Engine Graph Application
UG1076 -
Enabling Third-Party Simulators
UG1076 -
AI Engine Hardware Profile and Debug Methodology
UG1702 -
Debugging an AI Engine Application
XD100 -
Versal Emulation Waveform Analysis
XD100 -
AI Engine Debug with AI Engine Emulator
Performance Analysis and Optimization
UG1076 -
Performance Analysis of AI Engine Graph Application
UG1076 -
Profiling the NoC
UG1076 -
Latency and Throughput Estimates
XD100 -
AI Engine Performance and Deadlock Analysis Tutorial
XD100 -
Versal Emulation Waveform Analysis
Test Hardware and Debug the AI Engine Graph
Create a Verification Subsystem for Hardware Testing
UG1742 -
Installing the Vitis Platform
XD100 -
Versal Platform Creation Quick Start
XD100 -
AI Engine A-to-Z Flow for Linux
XD100 -
Creating a Bare Metal Verification Platform (A-to-Z Flow for Bare Metal)
Integrate AIE and Other Domains with the Verification Subsystem
UG1079 -
AI Engine/Programmable Logic Integration
UG1701 -
Building and Running the System
UG1702 -
Using the Vitis Unified IDE
UG1076 -
Programming the PS Host Application
UG1701 -
Getting Started with Vitis
Xilinx Runtime Library (XRT)
UG1642 -
AI Engine Software Driver Reference Manual
XD100 -
Versal AI Engine Integration Tutorial
XD100 -
Post-Link Recompile of an AI Engine Application
XD100 -
AI Engine Compiler Features
XD100 -
RTL / AI Engine interfacing Examples
XD100 -
Vitis Export To Vivado
Validate Subsystem Using Hardware Emulation
UG1076 -
Validate the Subsystem Using Hardware Emulation
UG1702 -
Debugging the System Project and AI Engine Components
UG1076 -
Performance Analysis of the AI Engine Graph Applicaton
XD100 -
AI Engine Debug with Hardware Emulator
XD100 -
Versal Emulation Waveform Analysis
XD100 -
AI Engine Performance and Deadlock Analysis Tutorial
Test and Debug AIE Graph in Hardware
UG1701 -
Stage 1: Design Execution and System Metrics
UG1701 -
Stage 2: System Profiling
UG1701 -
Stage 3: PL Kernel Analysis
UG1701 -
Stage 4: AI Engine Event Trace and Analysis
UG1701 -
Stage 5: Host Application Debug
AI Engine Test Harness
XD100 -
AI Engine Debug in Hardware
XD100 -
LeNet CNN 1x Example Design Tutorial
XD100 -
AI Engine Performance and Deadlock Analysis Tutorial
Overview
Overview
Training Modules
Develop AI Engine Kernels and Graph
Versal Design Partitioning (incl. AI Engine Array)
Libraries for AI Engine-ML
Develop the AI Engine Kernel and Graph
Verify the Algorithm, Test, and Validate AI Engine Kernels in Vitis
Simulate and Debug the AI Engine Graph
Debugging
Performance Analysis and Optimization
Test Hardware and Debug the AI Engine Graph
Create a Verification Subsystem for Hardware Testing
Integrate AIE and Other Domains with the Verification Subsystem
Validate Subsystem Using Hardware Emulation
Test and Debug AIE Graph in Hardware
Overview
Overview
XD100 -
Vitis Tutorials: AI Engine Development
AI Engine web page
AI Engine Series Articles
AR75837 -
AI Engine Solution Center
AR75790 -
AIE Compiler - General Guidance and Known Issues
AR75788 -
AIE Simulator - General Guidance and Known Issues
Training Modules
Designing with Versal AI Engine: Quick Start
Designing with Versal AI Engine 1: Architecture and Design Flow
Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
Designing with Versal AI Engine 3: Kernel Programming and Optimization
Develop AI Engine Kernels and Graph
Versal Design Partitioning (incl. AI Engine Array)
UG1273 -
System Design Methodology
AM020 -
Versal Adaptive SoC AIE-ML Architecture Manual
UG1504 -
System Design Planning Methodology Flow
XD100 -
Polyphase Channelizer
Libraries for AI Engine-ML
DSP Library
Vision Libraries
Develop the AI Engine Kernel and Graph
UG1076 -
AI Engine Tools and Flows User Guide
UG1603 -
AI Engine-ML Kernel and Graph Programming Guide
UG1603 -
Block Floating Type (AIE-ML v2 only)
UG1603 -
AI Engine-ML Memory Tile Programming
UG1603 -
Examples on Memory and DMA Programming
UG1529 -
AI Engine API User Guide
UG1583 -
AI Engine-ML Intrinsics User Guide
UG1639 -
AI Engine-ML v2 Intrinsics
UG1603 -
Example Designs Using the AI Engine API
UG1603 -
Matrix Multiplications - mmul (AIE-ML v2 only)
UG1701 -
Vitis Functional Simulation
UG1701 -
Vitis Subsystem Flow
XD100 -
AI Engine-ML Programming
XD100 -
A to Z Bare-metal Flow
XD100 -
AI Engine Compiler Features
XD100 -
Using GMIO
XD100 -
Runtime Parameter Reconfiguration
XD100 -
Packet Switching Tutorial
XD100 -
AI Engine Versal Integration
XD100 -
Prime Factor FFT-1008 on AIE-ML
XD100 -
AI Engine-ML LeNet Tutorial
XD100 -
MNIST ConvNet on AIE-ML
XD100 -
Softmax Function
XD100 -
Polyphase Channelizer on AIE-ML using Vitis Libraries
Verify the Algorithm, Test, and Validate AI Engine Kernels in Vitis
UG1076 -
Simulating an AI Engine Graph Application
Simulate and Debug the AI Engine Graph
Debugging
UG1076 -
Compiling an AI Engine Graph Application
UG1076 -
Simulating an AI Engine Graph Application
UG1702 -
Enabling Third-Party Simulators in the Vitis IDE
UG1076 -
Profiling the AI Engine
UG1701 -
Hardware Profile and Debug Methodology
UG1702 -
Debugging the System Project and AI Engine Components
Performance Analysis and Optimization
UG1076 -
Performance Analysis of AI Engine Graph Application
UG1076 -
Throughput and Latency Estimates
XD100 -
Versal Emulation Waveform Analysis
Test Hardware and Debug the AI Engine Graph
Create a Verification Subsystem for Hardware Testing
UG1701 -
Creating and Using Vitis Platforms
XD098 -
Versal Platform Creation Quick Start
XD100 -
A to Z Bare-metal Flow
Integrate AIE and Other Domains with the Verification Subsystem
UG1603 -
AI Engine/Programmable Logic Integration
UG1701 -
Building and Running the System
UG1702 -
Using the Vitis IDE
UG1076 -
Programming the PS Host Application
Xilinx Runtime Library (XRT)
UG1642 -
AI Engine System Software Driver Reference Manual
Validate Subsystem Using Hardware Emulation
UG1701 -
Running the System on Embedded Processor Platform
UG1393 -
Debugging the System Project and AI Engine Components
UG1076 -
Performance Analysis of the AI Engine Graph Applicaton
Test and Debug AIE Graph in Hardware
UG1701 -
Stage 1: Design Execution and System Metrics
UG1701 -
Stage 2: System Profiling
UG1701 -
Stage 3: PL Kernel Analysis
UG1701 -
Stage 4: AI Engine Event Trace and Analysis
UG1701 -
Stage 5: Host Application Debug
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