Introduction
Dynamic Function eXchange Home Page
UG909 - Vivado Design Suite User Guide: Dynamic Function eXchange
UG947 - Vivado Design Suite Tutorial: Dynamic Function eXchange
Key Concepts
UG909 - Overview of the Dynamic Function eXchange Software Flow
UG909 - Vivado Design Suite Project Flow
UG909 - Integrator Using Block Design Containers
UG909 - Design Considerations and Guidelines for Dynamic Function eXchange with Versal Adaptive SoC Devices
UG909 - Design Considerations and Guidelines for UltraScale and UltraScale+ Devices
UG909 - Design Considerations and Guidelines for Dynamic Function eXchange with 7 Series Devices
Frequently Asked Questions
UG909 - Can I partially reconfigure the NOC in the Versal NoC?
UG909 - How Do I Floorplan My Reconfigurable Modules?
UG909 - How Do I Program the Full and Partial BIT files?
UG909 - Can I Use Vivado Debug Cores in a Dynamic Function eXchange Design?
AR59964 - How Do I Use the SNAPPING_MODE Property?
AR64761 - How Do I Load a Bitstream Across the PCI Express Link in UltraScale Devices for Tandem PCIe and Partial Reconfiguration
AR61200 - How Do I Manually Control the Placement of the PartPins?

Videos	Design Files
Block Design Containers for DFX
Abstract Shell for DFX
Nested DFX
Dynamic Function eXchange Training Series: Floorplanning
Dynamic Function eXchange Training Series: Advanced Floorplanning
Partial Reconfiguration for UltraScale+
Partial Reconfiguration for UltraScale
Partial Reconfiguration in Vivado (7 Series)
Dynamic Function eXchange IP	Design Files
Dynamic Function eXchange Controller Product Page
Dynamic Function eXchange Decoupler Product Page
Dynamic Function eXchange AXI Shutdown Manager Product Page
Dynamic Function eXchange Bitstream Monitor Product Page
Tools and Examples	Design Files
GitHub - Versal Architecture-Specific DFX Tutorials
GitHub - DFX-MGR
GitHub - libdfx
Application Notes	Design Files
XAPP1338 - Fast Partial Reconfiguration Over PCI Express	Design Files
XAPP1335 - Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs Application Note
XAPP1292 - Loading Partial Bitstreams using TFTP	Design Files
XAPP1231 - Partial Reconfiguration of a Hardware Accelerator with Vivado	Design Files
XAPP1261 - Demonstration of Soft Error Mitigation IP and Partial Reconfiguration Capability on Monolithic Devices	Design Files
XAPP1099 - Local Partial Reconfiguration Using Embedded Processing for 3D ICs	Design Files
XAPP888 - MMCM and PLL Dynamic Reconfiguration	Design Files
White Papers	Design Files
WP534 - Technology Advancements for Dynamic Function eXchange in Vivado ML Edition
WP533 - Solution Efficiencies for Dynamic Function eXchange Using Abstract Shells

Software User Guides
UG894 - Vivado Design Suite User Guide: Using Tcl Scripting
UG899 - Vivado Design Suite User Guide: I/O and Clock Planning
UG901 - Vivado Design Suite User Guide: Synthesis
UG904 - Vivado Design Suite User Guide: Implementation
UG906 - Vivado Design Suite User Guide: Design Analysis and Closure Techniques
UG908 - Vivado Design Suite User Guide: Programming and Debugging
Reference Guides
UG835 - Vivado Design Suite Tcl Command Reference Guide
UG975 - Vivado Design Suite Quick Reference Guide
Training
Designing with DFX Using the Vivado Design Suite

Known Issues
UG909 - Known Issues and Limitations When Using Dynamic Function eXchange in Vivado
Forums
Forums - Advanced Flows And Hierarchical Design