| Register Name | DMA_BD1_2 |
|---|---|
| Offset Address | 0x00000A0028 |
| Absolute Address |
The notation for the AI Engine register addresses is aie_[pl]/[core]/[memory]/[noc]_module_column_row. |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | DMA BD1 2 |
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TLAST_Suppress | 31 | rwNormal read/write | 0 | MM2S channel - when set suppress assert of TLAST at the end of transfer |
| D0_Wrap | 26:17 | rwNormal read/write | 0 | Wrap after this many dim0 steps (32-bit words) and increment dim1 by a step. 0=do not wrap |
| D0_Stepsize | 16:0 | rwNormal read/write | 0 | Offset each step for dimension 0 (number of 32-bit words) (actual -1); Range [1:128k] |